XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 40

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

XR17C158
5V PCI BUS OCTAL UART
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode. A receive data timeout interrupt
will be issued in the FIFO mode when the receive FIFO has not reached the programmed trigger level and the
RX input has been idle for 4 character + 12 bit times.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
When Auto RS485 mode operation is disabled (FCTR bit-5 = 0), this interrupt is associated with bit-5 in the
LSR register. An interrupt is issued whenever the THR becomes empty or when data in the FIFO falls below
the programmed trigger level. When Auto RS485 mode operation is enabled (FCTR bit-5 = 1), this interrupt is
associated with bit-6 in the LSR register. An interrupt is issued whenever the TX FIFO and the TSR becomes
empty.
• Logic 0 = Disable Transmit Holding Register empty interrupt (default).
• Logic 1 = Enable Transmit Holding Register empty interrupt.
IER[2]: Receive Line Status Interrupt Enable
Any of LSR register bits 1, 2, 3 or 4 will generate an LSR interrupt immediately when a character received by
the RX FIFO has an error.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
IER[6]: RTS#/DTR# Output Interrupt Enable (requires EFR bit-4=1)
The RTS# or DTR# output is selected via MCR bit-2. See
• Logic 0 = Disable the RTS#/DTR# interrupt (default).
• Logic 1 = Enable the RTS#/DTR# interrupt. The UART issues an interrupt when the RTS#/DTR# pin makes
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
The CTS# or DSR# input is selected via MCR bit-2. See
• Logic 0 = Disable the CTS#/DSR# interrupt (default).
• Logic 1 = Enable the CTS#/DSR# interrupt. The UART issues an interrupt when CTS# pin makes a transi-
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR
will give the user the current highest pending interrupt level to be serviced with others queued up for next ser-
vice. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table,
Table
ated with each of these interrupt levels.
4.8.5
details.
a transition.
tion.
13, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associ-
Interrupt Status Register (ISR) - Read-Only
40
Table 10
Table 10
or MCR[2] for complete details.
or MCR[2] for complete details.
xr
REV. 1.4.3