M5275EVBE Freescale Semiconductor, M5275EVBE Datasheet - Page 10

• Manufacturer Part Number: M5275EVBE
• Description: MCF5274/75 EVALUATION BO
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5275EVBE

• Contents: Module and Misc Hardware
• Silicon Manufacturer: Freescale
• Core Architecture: Coldfire
• Core Sub-architecture: Coldfire V2
• Silicon Core Number: MCF52
• Silicon Family Name: MCF527x
• Rohs Compliant: Yes
• For Use With/related Products: MCF5274, MCF5275
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Recommendations
5.2.1
Figure 2
(PLLV
The relationship between SDV
SDV
5.2.1.1
If OV
output drivers connected to the OV
long after OV
SDV
protection diodes. The rise times on the power supplies should be slower than 1 μs to avoid turning on the
internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
10
1. Use 1 μs or slower rise time for all supplies.
2. V
DD
DD,
DD
DD
ramps with OV
use a low drop-out voltage regulator.
(2.5V or 3.3V) and OV
/SDV
or PLLV
shows situations in sequencing the I/O V
DD
), and Core V
Supply Voltage Sequencing and Separation Cautions
/PLLV
Power Up Sequence
DD
DD
/SDV
DD
are powered up with V
3.3V
2.5V
1.5V
DD
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
by more than 0.4 V during power ramp-up or high current will be in the internal ESD
Notes:
0
Figure 2. Supply Voltage Sequencing and Separation Cautions
DD
and OV
DD
DD
1.
2.
3.
4.
/SD V
VDD should not exceed OVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
Recommended that VDD should track OVDD/SDVDD/PLLVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD, SDVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
powers up before V
(V
DD
DD
1
DD
DD
DD
).
/SDV
and OV
2
DD
going to the higher external voltages. One way to accomplish this is to
are specified relative to V
/SDV
DD
DD
DD
should track up to 0.9 V, then separate for the completion of
DD
Supplies Stable
at 0 V, then the sense circuits in the I/O pads cause all pad
is non-critical during power-up and power-down sequences.
DD
to be in a high impedance state. There is no limit on how
must powered up. V
DD
(OV
DD
), SDRAM V
DD
.
DD
OV
V
SDV
should not lead the OV
DD
DD
DD
,
DD
, SDV
(SDV
(2.5V)
DD
Time
DD
Freescale Semiconductor
, PLLV
), PLL V
DD
DD
DD
,