M5275EVBE Freescale Semiconductor, M5275EVBE Datasheet - Page 34

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M5275EVBE

Manufacturer Part Number
M5275EVBE
Description
MCF5274/75 EVALUATION BO
Manufacturer
Freescale Semiconductor
Series
ColdFire®r
Type
Microprocessorr
Datasheet

Specifications of M5275EVBE

Contents
Module and Misc Hardware
Silicon Manufacturer
Freescale
Core Architecture
Coldfire
Core Sub-architecture
Coldfire V2
Silicon Core Number
MCF52
Silicon Family Name
MCF527x
Rohs Compliant
Yes
For Use With/related Products
MCF5274, MCF5275
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Electrical Characteristics
8.11
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
8.11.1
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_RXCLK frequency.
Table 18
Figure 16
8.11.2
Table 19
The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_TXCLK frequency.
34
Num
M1
M2
M3
M4
lists MII receive channel timings.
lists MII transmit channel timings.
Fast Ethernet AC Timing Specifications
shows MII receive signal timings listed in
FECn_RXDV
FECn_RXER
FECn_RXD[3:0] (inputs)
FECn_RXCLK (input)
MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK)
MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
FECn_TXER, FECn_TXCLK)
FECn_RXD[3:0], FECn_RXDV, FECn_RXER to FECn_RXCLK
setup
FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV, FECn_RXER
hold
FECn_RXCLK pulse width high
FECn_RXCLK pulse width low
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Figure 16. MII Receive Signal Timing Diagram
Characteristic
Table 18. MII Receive Signal Timing
M1
M2
M3
Table
18.
M4
35%
35%
Min
5
5
Max
65%
65%
Freescale Semiconductor
FECn_RXCLK
FECn_RXCLK
period
period
Unit
ns
ns

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