DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 35

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 6: Board Test System
Using the Board Test System
August 2010 Altera Corporation
Performance Indicators
These controls display current transaction performance analysis information collected
since you last pressed Start:
■
■
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■
■
■
■
Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 2 to
16,777,216.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■
■
Write, Read, and Total performance bars—Show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of
data analyzed per second. The top port data bus is 16 bits wide and the frequency
is 533 MHz double data rate (1066 Mbps per pin), equating to a theoretical
maximum bandwidth of 2132 MBps. The bottom port data bus is 64 bits wide and
the frequency is 533 MHz double data rate (1066 Mbps per pin), equating to a
theoretical maximum bandwidth of 8528 MBps.
1
Detected errors—Displays the number of data errors detected in the hardware.
Inserted errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
PRBS—Selects pseudo-random bit sequences.
Memory—Selects a generic data pattern stored in the on chip memory of the
Stratix IV GX device.
Performance figures are based on a 100-MHz input clock from
programmable oscillator X6. Using the
adjust the frequency changes the circuit speed in real time and the DDR3
tab performance indicators, which are capped at 100% for increased
frequencies. Physical layer speeds equal the oscillator X6 frequency times
the input PLL multiplier ratio. The default is 533 MHz (100 MHz × 5.33) or
1066 Mbps per pin. Changing the oscillator X6 frequency to 125 MHz
changes the circuit speed to 667 MHz or 1333 Mbps per pin. Typically you
need to reset the DDR3 design after changing the clock frequency.
“The Clock Control” on page 6–22
Stratix IV GX FPGA Development Kit User Guide
6–11
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