DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 37

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 6: Board Test System
Using the Board Test System
August 2010 Altera Corporation
Port
The Port control directs communication to one of two QDR II+ ports on your board.
Start
The Start control initiates QDR II+ memory transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■
■
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■
■
■
■
Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 2 to
1,048,576.
Write and Read performance bars—Show the percentage of maximum theoretical
data rate that the requested transactions are able to achieve.
Write (MBps) and Read (MBps)—Show the number of bytes of data analyzed per
second. The QDR II+ buses are 18 bits wide for both read and write, and the
frequency is 400 MHz double data rate (800 Mbps per pin), equating to a
theoretical maximum bandwidth of 1800 MBps, and 3600 MBps for simultaneous
read and write.
1
Detected errors—Displays the number of data errors detected in the hardware.
Inserted errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
Performance figures are based on a 100-MHz input clock from
programmable oscillator X6. Using the
adjust the frequency changes the circuit speed in real time and the QDR II+
tab performance indicators, which are capped at 100% for increased
frequencies. Physical layer speeds equal the oscillator X6 frequency times
the input PLL multiplier ratio. The default is 400 MHz (100 MHz × 4.00) or
800 Mbps per pin. Changing the oscillator X6 frequency to 125 MHz
changes the circuit speed to 500 MHz or 1000 Mbps per pin. Typically you
need to reset the QDR II+ design after changing the clock frequency.
“The Clock Control” on page 6–22
Stratix IV GX FPGA Development Kit User Guide
6–13
to