DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 48

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

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Configuring the FPGA Using the Quartus II Programmer
Stratix IV GX FPGA Development Kit User Guide
1
Target Frequency
The Target frequency control allows you to specify the frequency of the clock. Legal
values are between 10 and 810 MHz with eight digits of precision to the right of the
decimal point. For example, 421.31259873 is possible within 100 parts per million
(ppm). The Target frequency control works in conjunction with the Set New
Frequency control.
Reset Si570
The Reset Si570 control sets the Si570 programmable oscillator to the default
frequency of 100 MHz.
Set New Frequency
The Set New Frequency control sets the Si570 programmable oscillator frequency to
the value in the Target frequency control. Frequency changes might take several
milliseconds to take effect. You might see glitches on the clock during this time. Altera
recommends resetting the FPGA logic after changing frequencies.
You can use the Quartus II Programmer to configure the FPGA with a specific SRAM
Object File (.sof). Before configuring the FPGA, ensure that the Quartus II
Programmer and the USB-Blaster driver are installed on the host computer, the USB
cable is connected to the FPGA development board, power to the board is on, and no
other applications that use the JTAG chain are running.
To configure the Stratix IV GX FPGA, perform the following steps:
1. Start the Quartus II Programmer.
2. Click Add File and select the path to the desired .sof.
3. Turn on the Program/Configure option for the added file.
4. Click Start to download the selected file to the FPGA. Configuration is complete
Using the Quartus II programmer to configure a device on the board causes other
JTAG-based applications such as the Board Test System and the Power Monitor to
loose their connection to the board. Restart those applications after configuration is
complete.
when the progress bar reaches 100%.
Configuring the FPGA Using the Quartus II Programmer
August 2010 Altera Corporation
Chapter 6: Board Test System