HSP50210JI-52Z Intersil, HSP50210JI-52Z Datasheet
HSP50210JI-52Z
Specifications of HSP50210JI-52Z
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HSP50210JI-52Z Summary of contents
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... All other trademarks mentioned are the property of their respective owners. HSP50210 July 2, 2008 FN3652.5 LOCK DETECT LKINT LEVEL DETECT THRESH A OUT(9-0) MAGNITUDE 8 10 CARTESIAN PHASE 8 TO POLAR SLICER B OUT(9- SMBLCLK OEA OEB | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2008. All Rights Reserved ...
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... HSP50210JC-52Z HSP50210JI-52 HSP50210JI-52 HSP50210JI-52Z (Note) HSP50210JI-52Z NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Pin Description NAME TYPE VCC - +5V Power Supply. GND - Ground. IIN9-0 I In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are sampled by CLK when the SYNC signal is ...
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Pin Description (Continued) NAME TYPE OEA I A Output Enable. This pin is the three-state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high impedance. OEB I B Output Enable. This pin is the three-state control ...
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LEVEL HI/LO DETECT SYNC SYNTHESIZER/ M MIXER IIN9-0 U QIN9 SSYNC M U SERCLK X ISER QSER NCO SOFSYNC SOF SERIAL COFSYNC OUTPUT COF FORMATTER SLOCLK 8 C7-0 WR MICROPROCESSOR RD INTERFACE A2-0 CLK FRZ_ST FRZ_CT FIGURE ...
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Functional Description The HSP50210 Digital Costas Loop (DCL) contains most of the baseband processing functions needed to implement a digital Costas Loop Demodulator. These functions include LO generation/mixing, matched filtering, AGC, carrier phase and frequency error detection, timing error detection, ...
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REGISTER ENABLE RATE @ = SYNC RATE * = TWICE SYMBOL RATE ! = SYMBOL RATE BLANK = CLK RATE MATCHED FILTERING HI/LO REG NCO MIXER REG BYPASS MIXER BYPASS RRC ...
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NCO/Mixer The NCO/Mixer performs a complex multiply between the baseband input and the output of a quadrature NCO (Numerically Controlled Oscillator). When the HSP50210 (DQT) is used with the HSP50110 (DCL), the NCO/Mixer shortens the Carrier Tracking Loop (i.e., minimizes ...
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CLK CLK CLK FREQUENCY (NORMALIZED TO INPUT SAMPLE RATE) FIGURE 4. RRC FILTER IN HSP50210 0 -0.18 -0.36 SHOWN BELOW ENLARGED FOR CLARITY -0.54 -0.72 -0.90 f ...
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The phase conversion is equivalent to Equation 6: 1 – ⁄ ), Phase (I, Q) tan = -1 where tan ( ) is the arctangent function. The phase conversion output is an 8-bit two’s complement output, which ...
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Soft Decision Slicer to yield optimum performance. Note: Failure to consider the variations due to noise or interfering signals, can result in signal limiting in the HSP50210 processing algorithms, which will ...
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AGC LOOP FILTER AGC AGC UPPER LOWER LIMIT † LIMIT † READ E M REG AGC GAIN = (1 1.0000 TO 15.8572 = 24dB) GAIN ADJUST ...
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TABLE 4. AGC GAIN MANTISSA TO DECIMAL MAPPING DECIMAL VALUE BINARY CODE OF AGC BINARY CODE (MMMMMM ) MANTISSA (MMMMMM AGC 000000 0.000000 100000 000001 0.015625 100001 000010 0.031250 100010 000011 0.046875 100011 000100 0.062500 100100 000101 0.078125 100101 000110 ...
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Loop Gain, accumulated in the loop filter, limited and output to the gain adjusters. The AGC loop tries to make the error correction as quickly as possible, but is limited by the AGC Loop Gain and potentially, the AGC limits. ...
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TO 1.9844 (0.0156 STEPS) SYNTHESIZER/ MIXER G = 1.0, 0.5 (NOTE 1.0, 1.13 (NOTE 2) PART INPUT (NOTE BINARY POINT - - RND INPUT TO ...
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REGISTER ENABLE RATE ! = SYMBOL RATE BLANK = CLK RATE R FRZ_ST E G SAMPLING ERROR DETECTOR ‘0’ TRANSITION MUX DETECT I DATA END DECISION TRANSITION MID-POINT - + I MID MID-SYMBOL ‘0’ ! TRANSITION MUX DETECT Q DATA ...
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Sampling Error Detector The Sampling Error Detector is a decision based error detector which determines sampling errors on both the I and Q processing paths. The detector assumes that it is fed with samples of the baseband waveform taken in ...
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HARD DECISION THRESHOLD ‘1’ DECISION ‘0’ DECISION ‘1’ STRONGER WEAKER WEAKER -0.5 0.0 FS MSB-1 1/2 MSB 1/3 MSB-1 0 MSB-1 1/3 MSB 1/2 MSB-1 -FS FIGURE 13. OVERLAY OF THE HARD/SOFT DECISION THRESHOLDS ON THE SYMBOL PROBABILITY DENSITY FUNCTIONS ...
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In applications where Phase Error terms are generated faster than the processing rate of the Carrier Loop Filter, an error accumulator is provided to accumulate errors until the loop filter is ready for a new input. Phase Error terms are ...
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FRZ_CT CARRIER PHASE ERROR DETECT PHASE OFFSET + SHIFT SHIFT LEFT REG “0” PHASE ERROR θ INVERT DELAY PHASE * @ OR ( 16) ERROR - + DISCRIMINATOR “0” + ...
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TABLE 9. BIT WEIGHTING IN THE CARRIER LOOP FILTER TO THE NCO - TRACKING φ e BIT (AND MANTISSA WEIGHT ACCOM.) GAIN 40 39 Obtained with a shift of 31 and a Gain of 01.1111 (~ ...
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TABLE 10. BIT WEIGHTING IN THE CARRIER LOOP FILTER TO THE NCO - SWEEP BIT SWEEP φ WEIGHT e MANTISSA GAIN 40 39 Shift 27 and Gain = 01.1111 ...
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Frequency Sweep Block The Frequency Sweep Block is used during carrier acquisition to sweep the range of carrier uncertainty. The Sweep Block is loaded with a programmable value which is input to the lag path of the Carrier Tracking Loop ...
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State Machine (see Figure 16). The function of the Lock Detector is to monitor the baseband symbols and to decide whether the Carrier Tracking Loop is locked to the input signal. Note: The Symbol Tracking Loop locks independently; under most ...
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Search. The frequency uncertainty is swept by enabling the Frequency Sweep Block to the lag path of the Carrier Tracking Loop Filter. The acquisition parameters are enabled to the Loop Filters and the Lock Detector Accumulators. Phase lock is obtained ...
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PHASE ERROR ACCUMULATOR FINISHES BEFORE INTEGRATION COUNTER INTEGRATION COUNTER FINISHES BEFORE PHASE ERROR ACCUMULATOR Serial Output Controller The frequency correction terms generated by the Symbol and Carrier Loop Filters are output through two separate serial interfaces. The symbol frequency offset ...
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The status bit definition is shown in Table 11: TABLE 11. STATUS BIT DEFINITIONS STATUS BIT DEFINITION 6 Carrier Tracking Loop Lock 5 Acq/Trk 4 Frequency Sweep Direction 3 High Power 2 Low Power 1 Data Rdy To simplify the ...
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REGISTERS DEFINITION (4) 32-bit Carrier Loop Letter Lag Acc. Output (4) 32-bit Symbol Tracking Loop Letter Lag Acc. Output (1) 8-bit AGC Loop Letter Output 16-bit Lock Detector φe Acc. Output (2) (2) 16-bit Lock Detector GE Acc. Output ...
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A0-2 C0-7 CLK NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify that the processor waveforms meet the parameters in “Waveforms” on ...
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SR7=0 CLK SR HALT LD ENABLE AT END OF LD REG. CYCLE FOR READING NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will ...
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C0-7 CLK SR-7 LKINT NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify that the processor waveforms ...
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TABLE 15. DATA PATH CONFIGURATION CONTROL REGISTER BIT POSITION FUNCTION 31-27 Reserved Reserved. Set to 0 for proper operation. 26-24 Integrate/Dump Shifter These bits set the shifter attenuation in the Integrate/Dump Filter. Gain 000 = No Shift (Gain = 2 ...
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TABLE 16. POWER DETECT THRESHOLD CONTROL REGISTER BIT POSITION FUNCTION 31-8 Not Used No programming required. 7-0 Power Threshold The THRESH output is driven low when the magnitude output of the Cartesian-to-Polar Converter exceeds the threshold programmed here. The threshold ...
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TABLE 18. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER (Continued) BIT POSITION FUNCTION 5-2 Phase Offset These bits set the phase offset added (modulo 2 Converter. The phase offset is represented as a 4-bit fractional 2’s Complement value with the following ...
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TABLE 21. CARRIER LOOP FILTER CONTROL REGISTER #1 (Continued) BIT POSITION FUNCTION 5 Lead/Lag to Internal 0 = Sum of lead and lag paths routed to the internal NCO. (32 MSBs of sum are routed). NCO Routing 1 = The ...
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TABLE 25. CARRIER LOOP FILTER GAIN (ACQ) CONTROL REGISTER BIT POSITION FUNCTION 31-24 Not Used No programming required. 23-18 Reserved Reserved. Set to 0 for proper operation. 17-14 Carrier Lead Gain These bits are the 4 fractional bits of the ...
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TABLE 27. FREQUENCY SWEEP/ AFC LOOP CONTROL REGISTER (Continued) BIT POSITION FUNCTION 8-5 AFC Gain Mantissa Sets Frequency Error Gain. Format same as lead gain mantissa (see Table 25). Bit position 11 is the (Track) MSB. 4-0 AFC Gain Exponent ...
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TABLE 29. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER (Continued) BIT POSITION FUNCTION 8 Single/Double Rail This bit sets whether sampling error is derived from symbol transitions on just the I rail (single rail) or both Sampling Error the I and ...
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TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER (Continued) BIT POSITION FUNCTION 13-9 Symbol Tracking These bits set the lead gain exponent as given by: Lead Gain Exponent Symbol Tracking Lead Gain Exponent = 2 (Acquisition) where E ...
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TABLE 35. LOCK DETECTOR CONFIGURATION CONTROL REGISTER BIT POSITION FUNCTION 31-28 Reserved Reserved. Set to 0 for proper operation. 27 False Lock This bit selects the input to the False Lock Accumulator. Accumulator Operation 0 = Frequency Error input enabled ...
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TABLE 38. ACQUISITION/TRACKING CONTROL REGISTER BIT POSITION FUNCTION 31-16 Not Used No programming required. 15 Reserved Set to 0 for proper operation. 14 False Lock Detect This bit enables the false lock detection during the verify state of state machine ...
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TABLE 39. HALT LOCK DETECTOR FOR READING CONTROL REGISTER BIT POSITION FUNCTION N/A Stop Lock Detector for Writing this location halts the Lock Detector State Machine at the end of the current Lock Detector Reading Accumulator integration cycle. This function ...
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TABLE 42. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER (Continued) BIT POSITION FUNCTION 10 Serial Clock Phase 0 = Rising edge of serial clock at center of data bit. Relative to Data 1 = Falling edge of serial clock at center of ...
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TABLE 43. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER BIT POSITION FUNCTION 31-8 Not Used No programming required. 7-4 Reserved Set to zero for proper operation. 3-0 Output Select These bits select which input signals are routed to the 20 output ...
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TABLE 43. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER (Continued) BIT POSITION FUNCTION FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1), and CARPHERR(7:1) These signals are useful in applications that need these signals output at the symbol rate and available for hardwiring, rather than at the processor ...
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TABLE 45. INITIALIZE LOCK DETECTOR (μP CONTROL MODE) CONTROL REGISTER BIT POSITION FUNCTION N/A Initialization of Lock Loading the address register with this destination address pre-loads all of the Lock Detector Detector Accumulators Accumulators and resets the Integration Counters to ...
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Appendix A Noise Bandwidth Summary For a given decimation rate, the double-sided noise equivalent bandwidth is shown using various combinations of the CIC filter and the compensation filters in the HSP50110. Each combination of filters is also shown with INTE- ...
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... Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Temperature Range HSP50210JC (Commercial 0°C to +70°C HSP50210JI (Industrial .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. ...
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Electrical Specifications V = 5.0V ±5 MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Setup Time IIN9-0, QIN9-0, SYNC, FZ_CT, FZ_ST to ...
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Waveforms t WRL C0-7, A0-2 FIGURE 26. TIMING RELATIVE CLK t DS IIN9-0, QIN9-0, SYNC, FZ_CT, FZ_ST AOUT9-0, BOUT9-0, COF, COFSYNC, SOF, SOFSYNC, HI/LO, SMBLCLK, SLOCLK, LKINT, THRES SERCLK, WR C7-0 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...