HSP50210JI-52Z Intersil, HSP50210JI-52Z Datasheet - Page 15

• Manufacturer Part Number: HSP50210JI-52Z
• Description: IC DEMODULATOR COSTAS 84-PLCC
• Manufacturer: Intersil

Specifications of HSP50210JI-52Z

• Function: Demodulator
• Frequency: 52MHz
• Rf Type: AM, FM
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTES:
Gain Distribution
The gain distribution in the DCL is shown in Figure 10.
These gains consist of a combination of fixed,
programmable, and adaptive gains. The fixed gains are
introduced by processing elements such as the Mixer and
Square Root of Root Raised Cosine Filter. The adaptive
gains are set to compensate for variations in input signal
strength.
The main signal path, with processing block gains and path
bit weightings, is shown in Figure 10. The quadrature inputs
to the HSP50210 are 10-bit fractional two’s complement
numbers with relative bit weightings, as shown in Figure 10.
The first element in the processing chain is the Mixer, which
scales the quadrature outputs of the complex multiplier by
1/2 providing a gain of G = 0.5. If the Mixer is bypassed, the
signal is passed unmodified with a gain of 1.0. Following the
mixer, the quadrature signal is passed to the fixed coefficient
RRC filtering block, which has a gain of 1.13 if enabled and
1.0 if bypassed. Next, the AGC supplies gain to maintain an
optimal signal level at the input to the Soft Decision Slicer,
Cartesian-to-Polar Converter, and the Symbol Tracking
Loop. The gain supplied by the AGC ranges from 1.0 to
1.9844*2
1. If the Mixer is enabled, the result of the complex multiply is scaled by two (G = 0.5). If the mixer is bypassed, the data passes unmodified (G = 1.0).
2. If the Root Raised Cosine Filter is enabled, a gain of G = 1.13 is introduced. If the RRC filters bypassed, the gain is unity.
3. If the integrate and Dump Filter is bypassed the Sample Pair summer has a gain of G = 1.0 and the 2
4. The negative sign on the MSBs indicates use of 2’s complement data format.
and dump is enabled, the sample pair sum is scaled by one half (G = 0.5).
3
.
BINARY
POINT
G = 1.0, 0.5 (NOTE 1)
INPUT
PART
SYNTHESIZER/
INPUT TO CARTESIAN-TO-POLAR CONVERTER
MIXER
-2
2
2
-1
-9
0
(NOTE 4)
15
FIGURE 10. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS
G = 1.0, 1.13 (NOTE 2)
RND
2
-2
2
IF AGC OUTPUT SELECTED INPUT TO CARTESIAN-TO-POLAR CONVERTER
-10
-1
0
(0.0156 STEPS)
1.0 TO 1.9844
FILTER
MANTISSA
RRC
G = 1.0 - 1.9844*2
-2
RND
2
2
2
0
-1
-10
1
AGC GAIN
G
AGC
-2
2
2
2
2
2
2
2
EXPONENT
4
3
2
1
0
-1
-9
5
2
0
3
HSP50210
TO 2
M
L
T
I
I
ACCUMULATOR
8
/
3
RND
G = 1 TO 16
-2
2
2
INT/DUMP
-1
-7
0
Following the AGC, the signal path is limited to 8 bits and
passed through the Integrate and Dump Filter en route to the
Soft Decision Slicer and Symbol Tracking Block. The I and D
Filter uses an accumulator together with a sample pair summer
to achieve the desired decimation rate. The I and D shifter is
provided to compensate for the gain introduced by the I and D
Accumulator. The accumulator introduces gain equal to the
decimation factor R, and the shifter gain can be set to 1/R. For
example, if the I and D Filter decimation of 16 is chosen, the I
and D Accumulator will accumulate 8 samples before dumping,
which produces a gain of 8. Thus, for unity gain, the I and D
Shifter would be set for a gain of 2
is unity gain since its output is scaled by one-half.
Symbol Tracking
The symbol tracking loop adjusts the baseband sampling
frequency to force sampling of the baseband waveform at
optimal points for data decisions. The key elements of this loop
are the Sampling Error Detector and Symbol Tracking Loop
Filter shown in Figure 11. The output of these two blocks is a
frequency correction term which is used to adjust the baseband
sample frequency external to the HSP50210. In typical
applications, the frequency correction term is fed back to the
HSP50110 to adjust baseband sampling via the Resampling
NCO (see HSP50110 Datasheet).
IF INT/DUMP OUTPUT SELECTED
-2
2
2
2
2
2
2
-1
-7
4
3
2
1
0
G = 2
INT/DUMP
INTEGRATE AND
SHIFTER
DUMP FILTER
0
TO 2
2
-2
2
-11
2
2
2
2
-1
4
3
2
1
0
-4
M
L
T
I
I
G = 0.5, 1.0 (NOTE 3)
-2
2
2
-1
-6
0
SAMPLE PAIR
-7
SUMMER
-bit position is set to 1. If the integrate
-2
2
2
2
-1
-6
-7
0
-3
INPUT TO
SOFT DECISION
SLICER
AND
SYMBOL TRACKING
BLOCK
. The Sample Pair Summer
July 2, 2008
FN3652.5