HSP50210JI-52Z Intersil, HSP50210JI-52Z Datasheet - Page 13

• Manufacturer Part Number: HSP50210JI-52Z
• Description: IC DEMODULATOR COSTAS 84-PLCC
• Manufacturer: Intersil

Specifications of HSP50210JI-52Z

• Function: Demodulator
• Frequency: 52MHz
• Rf Type: AM, FM
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(MMMMMM
BINARY CODE
BINARY CODE
TABLE 5. AGC GAIN EXPONENT TO DECIMAL MAPPING
TABLE 4. AGC GAIN MANTISSA TO DECIMAL MAPPING
000000
000001
000010
000011
000100
000101
000110
001000
001001
001010
001011
001100
001101
010000
010001
010010
010011
010100
010101
010110
011000
011001
011010
000111
001110
001111
010111
011011
011100
011101
011110
011111
00
01
10
11
AGC
)
MANTISSA
DECIMAL
0.000000
0.015625
0.031250
0.046875
0.062500
0.078125
0.093750
0.109375
0.125000
0.140625
0.156250
0.171875
0.187500
0.203125
0.218750
0.234375
0.250000
0.265625
0.281250
0.296875
0.312500
0.328125
0.343750
0.359375
0.375000
0.390625
0.406250
0.421875
0.437500
0.453125
0.468750
0.484375
OF AGC
VALUE
DECIMAL/HEX
EXPONENT
0
1
2
3
13
(MMMMMM
BINARY CODE
100000
100001
100010
100100
100101
101000
101001
101010
100011
100110
100111
101011
101100
101101
101110
110000
110001
110010
110011
110100
110101
110110
111000
111001
111010
101111
110111
111011
111100
111101
111110
111111
DECIMAL SCALED
AGC
EXPONENT
)
MANTISSA
2
2
2
2
DECIMAL
0.500000
0.515625
0.531250
0.546875
0.562500
0.578125
0.593750
0.609375
0.625000
0.640625
0.656250
0.671875
0.687500
0.703125
0.718750
0.734375
0.750000
0.765625
0.781250
0.796875
0.812500
0.828125
0.843750
0.859375
0.875000
0.890625
0.906250
0.921875
0.937500
0.953125
0.968750
0.984375
OF AGC
0
1
2
3
VALUE
HSP50210
There are two techniques for setting a fixed gain for the
AGC. The first is to set Control Word 2 Bit 31 = 1. This
precludes any error update of present AGC gain value. The
second is to set the upper and lower AGC limits to the
desired gain using Figure 9. The upper and lower limits
have the same value for this case.
The HSP50210 provides two mechanisms for monitoring
signal strength. The first, which involved the THRESH
signal, has already been described. The second
mechanism is via the Microprocessor Interface. The 8 most
significant bits of the AGC loop filter output can be read by
a microprocessor. Refer to the “Microprocessor Interface”
on page 27 for details of how to read this value. This AGC
value has the format described in Figure 8.
AGC Bit Weighting and Loop Response
The AGC loop response is a function of the programmable
gain, the bit weightings inherent in the connection of each
element of the loop, the AGC Loop filter limits and the
magnitude of the input gain error step. Table 6 on page 14
details the bit weighting between each element of the AGC
Loop from the error detector through the weighting at the
gain adjuster in the signal path. The AGC Loop Gain sets the
growth rate of the sum in the loop filter accumulator. The
Loop filter output growth rate determines how quickly the
AGC loop traces the transfer function shown previously in
Figure 9. To calculate the rate at which the AGC can adjust
over a given period of time, a gain step is introduced to the
gain error detector and the amount of change that is
observed between clocks at the AGC Level Adjusters
(multipliers) is the AGC response time in dB per symbol.
This AGC loop will respond immediately with the greatest
correction term, then asymptotically approach zero
correction.
We begin calculation of the loop response with a full scale
error detector input of ±1. This error input is scaled by the
Cartesian to Polar converter, the error detector and the AGC
16
12
8
4
1
0
FIGURE 9. GAIN CONTROL TRANSFER FUNCTION
LINEAR ESTIMATE IN dB
(8 MSBs OF LOOP FILTER ACCUMULATOR)
GAIN CONTROL WORD
GAIN dB
LINEAR
GAIN
July 2, 2008
FN3652.5
24
18
12
6
0