HSP50210JI-52Z Intersil, HSP50210JI-52Z Datasheet - Page 27

• Manufacturer Part Number: HSP50210JI-52Z
• Description: IC DEMODULATOR COSTAS 84-PLCC
• Manufacturer: Intersil

Specifications of HSP50210JI-52Z

• Function: Demodulator
• Frequency: 52MHz
• Rf Type: AM, FM
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The status bit definition is shown in Table 11:
To simplify the output interface, a symbol clock (SMBLCLK)
is output which is synchronous to the soft bit decisions
produced by the Slicer. The SMBLCLK is a 50% duty cycle
clock whose rising edge is centered in the middle of the
output data period for both the soft bit decisions and the
end-symbol samples, as shown in Figure 20.
Microprocessor Interface
The Microprocessor Interface is used to write the
HSP50210’s Control Registers and monitor various read
points within the demodulator. Data written to the interface is
loaded into a set of four 8-bit holding registers, one Write
Address Register, or one Read Address Register. These
registers are accessed via the 3-bit address bus (A0-2) and
an 8-bit data bus (C0-7) as shown in Table 12. The R/W
column indicates whether the data is read from or written to
the given address.
R/W A2-0
TABLE 12. READ/WRITE ADDRESS MAP FOR
W
W
W
W
W
QSOFT2-0/
SMBLCLK
ISOFT2-0/
STATUS BIT
QEND7-1
IEND7-1/
000 Input Holding Register 0. Transfers to bits 7-0 of the
001 Input Holding Register 1. Transfers to bits 15-8 of the
010 Input Holding Register 2. Transfers to bits 23-16 of a
011 Input Holding Register 3. Transfers to bits 31-24 of the
100 Write Address Register. The register is loaded with the
6
5
4
3
2
1
FIGURE 20. OUTPUT DATA CLOCK TIMING
target control register. Bit 0 is the LSB of the target
register.
target control register.
32-bit target control register.
target control register. Bit 31 is the MSB of the 32-bit
register.
address of the control register targeted for update. The
address map for the control registers is given in
Tables 1C-32C.
Note: Addresses outside the range 0-31 are invalid.
TABLE 11. STATUS BIT DEFINITIONS
MICROPROCESSOR INTERFACE
Carrier Tracking Loop Lock
Acq/Trk
Frequency Sweep Direction
High Power
Low Power
Data Rdy
27
DESCRIPTION
DEFINITION
HSP50210
Data is read from an Internal Status Register and a series of
output holding registers. The output holding registers range
in size from 8 to 32 bits, and their contents are multiplexed
out a byte at a time on C7-0 by controlling A2-0 and
asserting RD. The addresses listed in Table 11 with the R
indicator provide the address map used for reading data
from the Microprocessor Interface.
Writing to the Microprocessor Interface
The HSP50210 is configured for operation by loading a set
of thirty-two control registers which range in size from 0 to
32 bits. They are loaded by first writing the configuration
data to the Microprocessor interface’s four holding registers
and then writing the target address to the Write Address
Register as shown in Figure 21. The Control Register
Address Map and bit definitions are given in Tables 14
through 45. The configuration data is transferred from the
holding registers to the target control register on the fourth
clock following a write to the address register. As a result,
the holding registers should not be updated any sooner
than 4 CLKs after an address register write (see Figure 21).
Note: The holding registers which map to the unused bits of
a particular control register do not have to be loaded.
Reading from the Microprocessor Interface
The Microprocessor Interface is used to monitor
demodulator operation by providing the ability to read the
accumulator contents in the Lock Detector and Loop
Filters. In addition, the interface is used to monitor the
HSP50210’s Internal Status Register. More clearly, the
following data is available to be read:
R/W A2-0
TABLE 12. READ/WRITE ADDRESS MAP FOR
W
R
R
R
R
R
101 Read Address Register. The address loaded into this
000 Selects output holding register bits 7-0 for output on
001 Selects output holding register bits 15-8 for output on
010 Selects output holding register bits 23-16 for output on
011 Selects output holding register bits 31-24 for output on
100 Multiplexes 8 bits of internal status out on C7-0. See
register specifies an internal read point as given the by
address map in Table 12. Addresses outside the range
0-4 are invalid.
C7-0 respectively. Bit 0 is the LSB of the internal holding
register.
C7-0, respectively.
C7-0, respectively.
C7-0, respectively. Bit 31 is the MSB.
Table 14 for bit map.
MICROPROCESSOR INTERFACE (Continued)
DESCRIPTION
July 2, 2008
FN3652.5