U3741BM-P2FL Atmel, U3741BM-P2FL Datasheet - Page 10

• Manufacturer Part Number: U3741BM-P2FL
• Description: IC RECEIVER PLL 300KHZ 20-SOIC
• Manufacturer: Atmel

Specifications of U3741BM-P2FL

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Remote Control Systems
• Current - Receiving: 8.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -

Polling Circuit and Control Logic
Basic Clock Cycle of the
Digital Circuitry
10
U3741BM
The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected micro-
controller. This flexibility enables the user to meet the specifications in terms of current
consumption, system response time, data rate etc.
Regarding the number of connection wires to the microcontroller, the receiver is very
flexible. It can be either operated by a single bi-directional line to save ports to the con-
nected microcontroller, it can be operated by up to three uni-directional ports.
The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 7, this clock cycle T
(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys-
tal oscillator (f
operating frequency of the local oscillator (f
Figure 7. Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
the following application-relevant parameters:
•
•
•
•
•
Most applications are dominated by two transmission frequencies: f
mainly used in the USA, f
T
each parameter.
Clk
-dependent parameters, the electrical characteristics display three conditions for
Timing of the polling circuit including bit check
Timing of analog and digital signal processing
Timing of register programming
Frequency of the reset marker
F filter center frequency (f
XTO
) is defined by the RF input signal (f
Send
Divider
:14/:10
XTO
= 433.92 MHz in Europe. In order to ease the usage of all
IF0
T
f
)
XTO
Clk
16
15
14
MODE
XTO
DVCC
LO
).
Clk
H: Europe (:14)
L : USA (:10)
is derived from the crystal oscillator
RFin
) which also defines the
Send
Clk
= 315 MHz is
4662B–RKE–10/04
. T
Clk
controls