U3741BM-P2FL Atmel, U3741BM-P2FL Datasheet - Page 13

• Manufacturer Part Number: U3741BM-P2FL
• Description: IC RECEIVER PLL 300KHZ 20-SOIC
• Manufacturer: Atmel

Specifications of U3741BM-P2FL

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Remote Control Systems
• Current - Receiving: 8.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -

Figure 9. Timing Diagram for a Completely Successful Bit Check
Bit Check Mode
Configuring the Bit Check
4662B–RKE–10/04
Bit check
Dem_out
Enable IC
DATA
Number of Checked Bits: 3
Polling mode
In bit check mode, the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subse-
quent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of this edge-to-edge
test, before the receiver switches to receiving, mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to the receiving mode due to noise. In the presence of a valid transmitter signal,
the bit check takes less time if N
check time is not dependent on N
tested successfully and the data signal is transferred to pin DATA.
According to Figure 10, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time t
the upper bit check limit T
T
switches to sleep mode.
Figure 10. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between T
T
preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good
choice in this regard. A good compromise between receiver sensitivity and susceptibility
to noise is a time window of ±25% regarding the expected edge-to-edge time t
preburst patterns that contain various edge-to-edge time periods, the bit check limits
must be programmed according to the required span.
Lim_max
Lim_min
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
or t
Bitcheck
1/2 Bit
ee
exceeds T
in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge
1/2 Bit
Dem_out
1/2 Bit
Bitcheck
Lim_max
Lim_max
Bit check ok
1/2 Bit
is set to a higher value, the receiver is less likely to
Bitcheck
, the bit check will be terminated and the receiver
Bitcheck
, the check will be continued. If t
T
T
ee
lim_min
lim_max
t
1/2 Bit
ee
is in between the lower bit check limit T
is set to a lower value. In polling mode, the bit
. Figure 9 shows an example where 3 bits are
1/2 Bit
1/f
Sig
Receiving mode
U3741BM
ee
is smaller than
Lim_min
Lim_min
ee
. Using
and
and
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