U3741BM-P2FL Atmel, U3741BM-P2FL Datasheet - Page 4

• Manufacturer Part Number: U3741BM-P2FL
• Description: IC RECEIVER PLL 300KHZ 20-SOIC
• Manufacturer: Atmel

Specifications of U3741BM-P2FL

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Remote Control Systems
• Current - Receiving: 8.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -

RF Front End
4
U3741BM
The RF front end of the receiver is a heterodyne configuration that converts the input
signal into a 1-MHz IF signal. According to the block diagram, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
oscillator) generates the drive voltage frequency f
the voltage at pin LF. f
to f
detector is connected to a passive loop filter and thereby generates the control voltage
V
equal to f
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-
tal. According to Figure 2, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f
of the crystal and XTO must be considered.
Figure 2. PLL Peripherals
The passive loop filter connected to pin LF is designed for a loop bandwidth of
B
LO. Figure 2 shows the appropriate loop filter components to achieve the desired loop
bandwidth. If the filter components are changed for any reason, please note that the
maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit
check may no longer be possible since f
starts to evaluate the incoming data stream. Therefore, self polling also does not work in
that case.
f
ing formula:
f
f
LO
XTO
LO
LF
Loop
is determined by the RF input frequency f
XTO
for the VCO. By means of that configuration, V
=
=
= 100 kHz. This value for B
f
RF
f
------- -
by the phase frequency detector. The current output of the phase frequency
64
LO
XTO
–
LO
f
IF
. If f
. When designing the system in terms of receiving bandwidth, the accuracy
LO
is determined, f
LO
is divided by a factor of 64. The divided frequency is compared
LFGND
LFVCC
DVCC
XTO
LF
Loop
XTO
V
V
exhibits the best possible noise performance of the
S
S
can be calculated using the following formula:
LO
C9
R1
RF
cannot settle in time before the bit check
and the IF frequency f
C10
LO
C
LF
L
is controlled in a way that f
for the mixer. f
XTO
C9 = 4.7 nF
C10 = 1 nF
R1 = 820
. The VCO (voltage-controlled
LO
IF
is dependent on
using the follow-
4662B–RKE–10/04
LO
XTO
/64 is
and