U3741BM-P2FL Atmel, U3741BM-P2FL Datasheet - Page 15

• Manufacturer Part Number: U3741BM-P2FL
• Description: IC RECEIVER PLL 300KHZ 20-SOIC
• Manufacturer: Atmel

Specifications of U3741BM-P2FL

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Remote Control Systems
• Current - Receiving: 8.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -

Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim
Duration of the Bit Check
Receiving Mode
Digital Signal Processing
4662B–RKE–10/04
(Lim_min = 14, Lim_max = 24)
Bit check
Counter
Enable IC
Bit check
Dem_out
Startup Mode
0
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for T
Characteristics”. T
baudrate range causes a lower value for T
in polling mode.
In the presence of a valid transmitter signal, T
that signal, f
thereby results in a longer period for T
preburst T
If the bit check has been successful for all bits specified by N
switches to receiving mode. According to Figure 9 on page 13, the internal data signal is
switched to pin DATA in that case. A connected microcontroller can be woken up by the
negative edge at pin DATA. The receiver stays in that condition until it is switched back
to polling mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud rate range (BR_Range). Figure 14 on page 16 illustrates how
Dem_out is synchronized by the extended clock cycle T
the bit check counter. Data can change its state only after T
edge-to-edge time period t
of T
The minimum time period between two edges of the data signal is limited to
t
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T
ceding edge-to-edge time interval t
specified bit check limits, the following level is frozen for the time period
T
relevant stable time period.
The maximum time period for DATA to be low is limited to T
ensures a finite response time during programming or switching off the receiver via pin
DATA. T
transmitter data stream. Figure 16 gives an example where Dem_out remains low after
the receiver has switched to receiving mode.
ee
DATA_min
1
XClk
T
2 3 4 5 6
DATA_min
.
DATA_L_max
= tmin1, in case of t
Preburst
Sig
7
. This implies an efficient suppression of spikes at the DATA output. At the
1
and the count of the checked bits, N
.
2
3
Bitcheck
4 5
is thereby longer than the maximum time period indicated by the
Bit check Mode
6 7 8 9
depends on the selected baud rate range and on T
ee
10
ee
of the Data signal as a result is always an integral multiple
1/2 Bit
1112
being outside that bit check limits T
13141516171819
ee
Lim_max)
as illustrated in Figure 15. If t
Bitcheck
DATA_min
Bitcheck
Bit check failed (CV_Lim = Lim_max)
20
requiring a higher value for the transmitter
21222324
Bitcheck
resulting in lower current consumption
is to some extent affected by the pre-
Bitcheck
is dependant on the frequency of
XClk
Bitcheck
. A higher value for N
. This clock is also used for
Sleep Mode
0
DATA_L_max
is given in “Electrical
DATA_min
Bitcheck
ee
XClk
U3741BM
is in between the
. This function
elapsed. The
, the receiver
= tmin2 is the
Clk
. A higher
Bitcheck
Bitcheck
15