NS16C2752TVSX/NOPB National Semiconductor, NS16C2752TVSX/NOPB Datasheet - Page 36

• Manufacturer Part Number: NS16C2752TVSX/NOPB
• Description: IC UART DUAL 64BYTE 48-TQFP
• Manufacturer: National Semiconductor

Specifications of NS16C2752TVSX/NOPB

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
Tx and Rx FIFO sizes
Supply voltage
Highest baud rate
Highest clock input frequency
Operating temperature
Enhanced Register Set
Sleep mode IER[4]
Xon, Xoff, and Xon-Any software auto flow control
CTS and RTS hardware auto flow control
Interrupt source ID in IIR
Tx FIFO trigger level select FCR[5:4]
IrDA v1.0 mode MCR[6]
Clock divisor 1 or 4 select MCR[7]
8.6 NOTES ON TX FIFO OF NS16C2752
Notes on interrupt assertion and deassertion.
1.
2.
To avoid frequent interrupt request generation, there is a
hysteresis of two characters. When the transmit FIFO
threshold is enabled and the number of empty spaces
reaches the threshold, a THR empty interrupt is
generated requesting the CPU to fill the transmit FIFO.
The host has to fill at least two characters in the Tx FIFO
before another THR empty interrupt can be generated.
The DMA request TXRDY works differently. When the
number of empty spaces exceeds the threshold,
TXRDY asserts initiating the DMA transfer. The TXRDY
deasserts when the transmit FIFO is full.
When the number of empty spaces reaches the threshold
level, an interrupt is generated. If the host does not fill the
FIFO, the interrupt will remain asserted until the host
writes to the THR or reads from IIR.
Features
TABLE 31. Differences among the UART products
4.5V to 5.5V
PC16552D
1.5Mbps
0 - 70°C
36
16-byte
24MHz
1 level
3-bit
No
No
No
No
No
No
3.
4.
5.
When the number of empty spaces reaches the threshold
level, an interrupt is generated. If the host reads the IIR
but does not fill the Tx FIFO, the INTR is deasserted.
However, if the host still does not fill the Tx FIFO, the
FIFO becomes empty. The THR empty interrupt is not
generated because the host has not written to the Tx
FIFO and the interrupt service is not complete.
When the number of empty spaces reaches the threshold
level, a THR empty interrupt is generated. If the host
writes at least one character into the Tx FIFO, the
interrupt is serviced and the THR empty flag is
deasserted. Subsequently, if the host fails to fill the FIFO
before it reaches empty, a THR empty interrupt will be
asserted.
Reset Tx FIFO causes a THR empty interrupt.
2.97V to 5.5V
NS16C2552
-40 to 85°C
5.0Mbps
16-byte
80MHz
1 level
5-bit
Yes
Yes
Yes
Yes
Yes
Yes
2.97V to 5.5V
NS16C2752
-40 to 85°C
5.0Mbps
64-byte
4 levels
80MHz
5-bit
Yes
Yes
Yes
Yes
Yes
Yes