A000046 Arduino, A000046 Datasheet - Page 97
A000046
Manufacturer Part Number
A000046
Description
MCU, MPU & DSP Development Tools Uno
Manufacturer
Arduino
Series
-r
Type
MCUr
Specifications of A000046
Processor To Be Evaluated
ATmega328
Interface Type
USB, I2C, SPI
Dimensions
2.7 in x 2.1 in
Operating Supply Voltage
5 V
Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega328
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- Download datasheet (13Mb)
14.5
8161D–AVR–10/09
Output Compare Unit
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation, see
Operation” on page
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max
and bottom signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation
Figure 14-3
Figure 14-3. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
shows a block diagram of the Output Compare unit.
bottom
FOCn
top
99.
OCRnx
ATmega48PA/88PA/168PA/328P
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
(”Modes of Operation” on page
COMnx1:0
TCNTn
OCFnx (Int.Req.)
OCnx
99).
”Modes of
97
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