MPC8536BVTATH Freescale Semiconductor, MPC8536BVTATH Datasheet - Page 62

• Manufacturer Part Number: MPC8536BVTATH
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1250
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATH

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1250 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB
Figure 35
2.11
This section provides the AC and DC electrical specifications for the USB interface of the MPC8535E.
62
At recommended operating conditions with OVDD is 3.3 V ± 5%.
EC_MDIO to EC_MDC hold time
EC_MDC rise time
EC_MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods +/-3ns. For
5. t
6. EC_MDC to EC_MDIO Data valid t
(reference)(state)
symbolizes management data timing (MD) for the time t
invalid (X) or data hold time. Also, t
signals (D) reach the valid state (V) relative to the t
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8535E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform
Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
That is, for a system running at a particular platform frequency (f
programmed between maximum f
MIIMCFG register section for more detail.
example, with a platform clock of 333MHz, the min/max delay is 48ns +/-3ns. Similarly, if the platform clock is 400MHz, the
min/max delay is 40ns +/-3ns).
time - Max Hold)
CLKplb_clk
Parameter/Condition
shows the MII management AC timing diagram.
USB
is the platform (CCB) clock
for inputs and t
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
EC_MDIO
EC_MDIO
EC_MDC
Table 45. MII Management AC Timing Specifications (continued)
(Output)
(Input)
Figure 35. MII Management Interface Timing Diagram
(first two letters of functional block)(reference)(state)(signal)(state)
MDC
MDDVKH
MDKHDV
= f
Symbol
t
MDDXKH
t
t
t
MDCR
MDHF
CCB
MDCH
symbolizes management data timing (MD) with respect to the time data input
is a function of clock period and max delay time t
/64 and minimum f
t
MDDVKH
1
t
MDC
MDC
t
MDKHDX
clock reference (K) going to the high (H) state or setup time. For rise
MDC
Min
—
—
0
from clock reference (K) high (H) until data outputs (D) are
MDC
CCB
t
MDCF
= f
), the EC_MDC output clock frequency can be
CCB
(first two letters of functional block)(signal)(state)
Typ
—
—
—
/448. See the MPC8536E reference manual’s
t
MDDXKH
t
MDCR
MDC
for outputs. For example, t
= 533/(2*4*8) = 533/64 = 8.3 MHz.
Max
10
10
—
MDKHDX
Freescale Semiconductor
. (Min Setup = Cycle
Unit
ns
ns
ns
CCB
). The actual
MDKHDX
Notes
—
—
—