MPC8536BVTATH Freescale Semiconductor, MPC8536BVTATH Datasheet - Page 96

• Manufacturer Part Number: MPC8536BVTATH
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1250
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATH

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1250 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Speed Serial Interfaces
Figure 64
driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8535E SerDes reference clock
input’s DC requirement, AC-coupling has to be used.
50Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending
on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor
to attenuate the LVPECL output’s differential peak level such that it meets the MPC8535E SerDes reference clock’s differential
input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential
peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67,
which requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible
with a particular clock driver chip.
Figure 65
levels of the clock driver are compatible with MPC8535E SerDes reference clock input’s DC requirement.
96
Single-Ended
CLK Driver Chip
Clock Driver
LVPECL CLK
Driver Chip
Clock Driver
Clock Driver
Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL
shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC
CLK_Out
CLK_Out
CLK_Out
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Figure 65. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω differential PWB trace
Total
output impedance is about 16 Ω.
R2
R2
50 Ω
100 Ω differential PWB trace
50
Ω. Assume clock driver’s
Figure 64
assumes that the LVPECL clock driver’s output impedance is
10nF
10 nF
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
50 Ω
50 Ω
50 Ω
50 Ω
Freescale Semiconductor
MPC8535E
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver