A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 109

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Typical Programming and Erase Times
References
Re-Programming the eNVM Blocks Using the Cortex-M3
In this mode the Cortex-M3 is executing the eNVM programming algorithm from eSRAM. Since individual
pages (132 bytes) of the eNVM can be write-protected, the programming algorithm software can be
protected from inadvertent erasure. When reprogramming the eNVM, both MSS I/Os and FPGA I/Os are
available as interfaces for sourcing the new eNVM image. The SoC Products Group provides working
example projects for SoftConsole, IAR, and Keil development environments. These can be downloaded
via the SoC Products Group Firmware Catalog.
Alternately, the eNVM can be reprogrammed by the Cortex-M3 via the IAP driver. This is necessary when
using an encrypted image.
Secure Programming
For background, refer to the Security in Low Power Flash Devices application note on the SoC Products
Group website. SmartFusion Secure ISP behaves identically to Fusion Secure ISP. Secure IAP of
SmartFusion devices is accomplished by using the IAP driver. Only the FPGA fabric and the eNVM can
be reprogrammed securely by using the IAP driver.
Table 4-3
devices, FPGA fabric and eNVM, using the SoC Products Group’s FlashPro hardware and software.
These times will be different for other ISP and IAP methods. The Program action in FlashPro software
includes erase, program, and verify to complete.
The typical programming (including erase) time per page of the eNVM is 8 ms.
Table 4-3 • Typical Programming and Erase Times
User’s Guides
DirectC User’s Guide
http://www.actel.com/documents/DirectC_UG.pdf
Fusion FGPA Fabric User’s Guide
http://www.actel.com/documents/Fusion_UG.pdf
Erase
Program
Verify
Chapters:
"In-System Programming (ISP) of Actel’s Low-Power Flash Devices Using FlashPro4/3/3X"
"Security in Low Power Flash Devices"
"Programming Flash Devices"
"Microprocessor Programming of Actel’s Low-Power Flash Devices"
documents the typical programming and erase times for two components of SmartFusion
A2F200
21
8
9
FPGA Fabric (seconds)
R e v i s i o n 6
A2F500
21
15
16
SmartFusion Intelligent Mixed Signal FPGAs
A2F200
N/A
18
26
eNVM (seconds)
A2F500
N/A
26
42
4 -7