A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 87

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Analog Specifications
Table 2-91 • Current Monitor Performance Specification
Specification
Input voltage range (for driving ADC
over full range)
Analog gain
Input referred offset voltage
Gain error
Overall Accuracy
Input referred noise
Common-mode rejection ratio
Analog settling time
Input capacitance
Input biased current
Power supply rejection ratio
Incremental
monitor
requirements (per current monitor
instance, not including ADC or
VAREFx)
Note:
Under no condition should the TM pad ever be greater than 10 mV above than the CM pad.
power
Current Monitor
Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply
voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit
mode and 91 Ksps, after digital compensation. All results are based on averaging over 16 samples.
operational
supply
current
current
From the differential voltage across the
input pads to the ADC input
Input referred offset voltage
–40ºC to +100ºC
Slope of BFSL vs. 50 V/V
–40ºC to +100ºC
Peak error from ideal transfer function,
25°C
0 VDC input (no output averaging)
0 V to 12 VDC common-mode voltage
To 0.1% of final value (with ADC load)
CM[n] or TM[n] pad,
–40°C to +100°C over maximum input
voltage range (plus is into pad)
DC (0 – 10 KHz)
VCC33A
VCC33AP
VCC15A
From CM_STB (High)
From ADC_START (High)
Strobe = 0; IBIAS on CM[n]
Strobe = 1; IBIAS on CM[n]
Strobe = 0; IBIAS on TM[n]
Strobe = 1; IBIAS on TM[n]
Test Conditions
R e v i s i o n 6
SmartFusion Intelligent Mixed Signal FPGAs
0 – 48
Min.
–86
0.3
41
0
0
5
5
Typical
±(0.1 +
0.25%)
0 – 50
±0.1
–87
150
140
0.1
0.1
0.4
50
42
50
8
0
1
2
1
±(0.4 +
1 – 51
1.5%)
Max.
±0.5
±0.5
200
0.5
0.5
0.5
mV plus
% nom.
% nom.
reading
mVrms
Units
V/V
mV
mV
mV
dB
pF
µA
µA
µA
µA
dB
µA
µA
µA
µs
µs
%
2- 75