A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 41

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The length of time an I/O can withstand I
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than 2200
operation hours to cause a reliability concern. The I/O design does not contain any short circuit
protection, but such protection would only be needed in extremely prolonged stress conditions.
Table 2-31 • Duration of Short Circuit Event before Failure
Table 2-32 • Schmitt Trigger Input Hysteresis
Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Temperature
–40°C
0°C
25°C
70°C
85°C
100°C
Input Buffer
LVTTL/LVCMOS
LVDS/B-LVDS/
M-LVDS/LVPECL
Note:
Input Buffer Configuration
3.3 V LVTTL / LVCMOS / PCI / PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board
noise. Microsemi SoC Products Group recommends signal integrity evaluation/characterization of
the system to ensure that there is no excessive noise coupling into input signals.
Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers
Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)
No requirement
No requirement
OSH
R e v i s i o n 6
/I
OSL
events depends on the junction temperature. The
Time before Failure
SmartFusion Intelligent Mixed Signal FPGAs
10 ns *
10 ns *
> 20 years
> 20 years
> 20 years
6 months
5 years
2 years
Hysteresis Value (typical)
240 mV
140 mV
80 mV
60 mV
20 years (100°C)
10 years (100°C)
Reliability
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