SAF-XC878CM-16FFI Infineon Technologies, SAF-XC878CM-16FFI Datasheet - Page 101
![MCU, 8BIT, 64K FLASH, 5V, 64LQFP](/photos/19/1/190186/ge64lqfp05-40_sml.jpg)
SAF-XC878CM-16FFI
Manufacturer Part Number
SAF-XC878CM-16FFI
Description
MCU, 8BIT, 64K FLASH, 5V, 64LQFP
Manufacturer
Infineon Technologies
Datasheet
1.SAF-XC878CM-16FFI.pdf
(146 pages)
Specifications of SAF-XC878CM-16FFI
Controller Family/series
XC800
Core Size
8bit
Program Memory Size
64KB
Ram Memory Size
3328Byte
No. Of Timers
4
No. Of Pwm Channels
10
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V To
Peripherals
ADC, PWM, Timer
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAF-XC878CM-16FFI 3V3 AA
Manufacturer:
Infineon Technologies
Quantity:
10 000
Company:
Part Number:
SAF-XC878CM-16FFI 3V3 AC
Manufacturer:
Infineon Technologies
Quantity:
10 000
Company:
Part Number:
SAF-XC878CM-16FFI 5V AA
Manufacturer:
Infineon Technologies
Quantity:
10 000
Part Number:
SAF-XC878CM-16FFI 5V AA
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
SAF-XC878CM-16FFI 5V AC
Manufacturer:
Infineon Technologies
Quantity:
10 000
Part Number:
SAF-XC878CM-16FFI5VAC
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
3.16
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
•
•
•
•
•
•
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 27
Data Sheet
Master and slave mode operation
– Full-duplex or half-duplex operation
Transmit and receive buffered
Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
clock
shows the block diagram of the SSC.
High-Speed Synchronous Serial Interface
92
Functional Description
XC878CLM
V1.2, 2009-11