SAF-XC878CM-16FFI Infineon Technologies, SAF-XC878CM-16FFI Datasheet - Page 113

• Manufacturer Part Number: SAF-XC878CM-16FFI
• Description: MCU, 8BIT, 64K FLASH, 5V, 64LQFP
• Manufacturer: Infineon Technologies

Specifications of SAF-XC878CM-16FFI

• Controller Family/series: XC800
• Core Size: 8bit
• Program Memory Size: 64KB
• Ram Memory Size: 3328Byte
• No. Of Timers: 4
• No. Of Pwm Channels: 10
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V To
• Peripherals: ADC, PWM, Timer
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.23
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
•
•
•
•
Features
•
•
•
•
•
The OCDS functional blocks are shown in
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
The OCDS system is accessed through the JTAG
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after XC878
1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
Data Sheet
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Use the built-in debug functionality of the XC800 Core
Add a minimum of hardware overhead
Provide support for most of the operations by a Monitor Program
Use standard interfaces to communicate with the Host (a Debugger)
Set breakpoints on instruction address and on address range within the Program
Memory
Set breakpoints on internal RAM address range
Support unlimited software breakpoints in Flash/RAM code region
Process external breaks via JTAG and upon activating a dedicated pin
Step through the program code
has been started in OCDS mode.
On-Chip Debug Support
104
Figure
32. The Monitor Mode Control (MMC)
1)
, which is an interface dedicated
Functional Description
XC878CLM
V1.2, 2009-11