SAF-XC878CM-16FFI Infineon Technologies, SAF-XC878CM-16FFI Datasheet - Page 97

• Manufacturer Part Number: SAF-XC878CM-16FFI
• Description: MCU, 8BIT, 64K FLASH, 5V, 64LQFP
• Manufacturer: Infineon Technologies

Specifications of SAF-XC878CM-16FFI

• Controller Family/series: XC800
• Core Size: 8bit
• Program Memory Size: 64KB
• Ram Memory Size: 3328Byte
• No. Of Timers: 4
• No. Of Pwm Channels: 10
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V To
• Peripherals: ADC, PWM, Timer
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following formulas calculate the final baud rate without and with the fractional divider
respectively:
The maximum baud rate that can be generated is limited to
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20 kHz to 57.6 kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 31
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 31
Baud rate
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated.
57.6 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
baud rate
lists the various commonly used baud rates with their corresponding parameter
=
Table 32
---------------------------------------------------------------------------------- - where 2
16 2
Typical Baud rates for UART with Fractional Divider disabled
×
baud rate
BRPRE
lists the resulting deviation errors from generating a baud rate of
Prescaling Factor
(2BRPRE)
1 (BRPRE=000
1 (BRPRE=000
2 (BRPRE=001
4 (BRPRE=010
×
f
=
PCLK
(
BR_VALUE
---------------------------------------------------------------------------------- -
16 2
×
BRPRE
B
B
B
B
+
×
)
)
)
)
f
PCLK
1
(
88
)
BR_VALUE
Reload Value
(BR_VALUE + 1)
156 (9C
156 (9C
156 (9C
78 (4E
H
BRPRE
H
H
H
)
)
)
)
+
1
f
)
PCLK
×
×
STEP
-------------- -
Functional Description
(
/32. Hence, for a module
256
BR_VALUE
Deviation Error
0.17 %
0.17 %
0.17 %
0.17 %
XC878CLM
V1.2, 2009-11
+
1
) 1
>
(3.4)
(3.5)