EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 665

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

DS785UM1
21.5.1 Example of the Bit Clock Generation.
21.5 I
For nBCG = 0 and BCR[1:0] = “10” the bit clock frequency is fixed at 64 times LRCK for word
lengths of 32 and 24 and at 32x LRCK for word lengths of 16. In the case of 24 and 32 bit
words, this 64x clock is then gating depending on the I
controller word size is 32, then all of the 64x clock pulses are passed. If the I
word size is 24, then the last 8 64x clock pulses are gated off in a LRCK cycle. For an I
controller word size of 16 than all of the 32x clock pulses are passed. This is shown in
Figure
For other values of nBCG and BCR, the register bit descriptions define the bit clock
operation.
2
S Bit Clock Rate Generation
21-2.
Output Data Bit
Align to SCLK Edge
Length
Table 21-4. I2SClkDiv SYSCON Register Effect on I
Ignored
Ignored
Ignored
Word
16
24
24
32
Function
(BCR[1:0])
Bit Clock
Rate
00
00
00
00
01
10
11
When SPOL=1 and
i2s_mstr_clk_cfg[3]=0, transition of
output data bit and LRCK align to falling
edge of SCLK
When SPOL=0 and
i2s_mstr_clk_cfg[3]=1, transition of
output data bit and LRCK align to rising
edge of SCLK;
Copyright 2007 Cirrus Logic
Table 21-5. Bit Clock Rate Generation
not Bit Clock
(nBCG)
Gating
Ignored
Ignored
Ignored
0 or 1
0 or 1
ORIDE=1
0
1
64x with last 8 cycles gated off in each word.
64x Note the last 8 cycles are not gated off.
Actual bit clock rate with respect to
2
2
S controller word size. If the I
S Clock Generation (Continued)
The output data bit is always a half-
cycle later to the SCLK edge which
aligns to LRCK transition. If the
SCLK rising edge is configured to
align to the LRCK transition, then
output data is aligned to falling edge
of SCLK. If the SCLK falling edge
aligns to the LRCK transition, then
output data aligns to the SCLK rising
edge.
Fixed at 128x
Fixed at 32x
Fixed at 64x
LRCK
32x
64x
ORIDE=0
EP93xx User’s Guide
2
S controller
I
2
S Controller
2
S
2
S
21-9
21