EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 703
![32-Bit Microcontroller IC](/photos/39/70/397001/bga352_sml.jpg)
EP9315-IBZ
Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IBZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1263
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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- Download datasheet (13Mb)
AC97IEx
AC97S1Data
DS785UM1
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
30
14
30
14
29
13
29
13
28
12
28
12
AC97IE1 - 0x8088_0018 - Read/Write
AC97IE2 - 0x8088_0038 - Read/Write
AC97IE3 - 0x8088_0058 - Read/Write
AC97IE4 - 0x8088_0078 - Read/Write
Interrupt Enable Register. The AC97IE registers control the Interrupt Enables
for the FIFOs within the controller. All bits are cleared on reset.
RSVD:
RIE:
TIE:
RTIE:
TCIE:
0x8088_0080 - Read/Write
Slot 1 Data Register. The AC97S1Data register is a read / write register. When
a write has occurred to this register, the data contained within it is sent on the
RSVD
27
11
27
11
26
10
26
10
RSVD
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved. Unknown During Read.
Receive Interrupt Enable - If this bit is set to “1”, the FIFO
receive interrupt is enabled.
Transmit Interrupt Enable - If this bit is set to “1”, the FIFO
transmit interrupt is enabled.
Receive Timeout Interrupt Enable - If this bit is set to “1”,
the FIFO receive timeout interrupt is enabled.
Transmit Complete Interrupt Enable - If this bit is set to “1”,
the FIFO transmit complete interrupt is enabled.
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
DATA
RIE
19
19
3
3
EP93xx User’s Guide
TIE
18
18
2
2
AC’97 Controller
RTIE
17
17
1
1
22-15
TCIE
16
16
0
0
22
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