AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 39

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To determine the external loop filter components, the user
decides on the desired open loop bandwidth (f
margin ( ). These parameters allow calculation of the loop filter
components, as follows:
where K
charge pump current (amperes), N is the programmed feedback
divider value, f
and Φ is the desired phase margin (in radians).
For example, assuming that N = 40, I
and Φ = 50°, then the loop filter calculations yield R1 = 3.31
kΩ, C1 = 330 pF, and C2 = 50.4 pF.
System Clock Period
Many of the user-programmable parameters of the AD9548 have
absolute time units. To make this possible, the AD9548 requires
a priori knowledge of the period of the system clock. To accom-
modate this requirement, the user programs the 21-bit nominal
system clock period in the nominal SYSCLK period register
(Address 0106 to Address 0108). The contents of this register
reflect the actual period of the system clock in femtoseconds.
The user must properly program this register to ensure proper
operation of the device because many of its subsystems rely on
this value.
System Clock Stability Timer
The system clock stability timer (Register 0106 to Register 0108) is
a 20-bit value programmed in milliseconds. If the programmed
timer value is 0, then the timer immediately indicates that it has
timed out. If the programmed timer value is a nonzero value
and the SYSCLK PLL is enabled, then the timer starts timing
when the SYSCLK PLL lock detector indicates lock and times
out after the prescribed period. However, when the user
disables the SYSCLK PLL, then the timer ignores the SYSCLK
PLL lock detector and starts timing as soon as the SYSCLK PLL
is disabled. The user can monitor the status of the stability timer
via Register 0D01, Bit 4, via the multifunction pins or via the
IRQ pin.
Note that the system clock stability timer must be programmed
before the SYSCLK PLL is either activated or disabled.
SYSCLK PLL Calibration
When using the SYSCLK PLL, it is necessary to calibrate the LC
VCO to ensure that the PLL can remain locked to the system
clock input signal. Assuming the presence of either an external
SYSCLK input signal or a crystal resonator, the calibration
process executes after the user sets and then clears the calibrate
C1
C2
R1
VCO
I
I
N
CP
CP
I
= 7 × 10
CP
Nf
2
2
K
K
N
K
OL
VCO
VCO
OL
f
VCO
OL
is the desired open-loop bandwidth (in hertz),
f
tan
OL
⎛
⎜
⎜
⎝
2
7
1
⎛
⎜
⎜
⎝
V/ns (typical), I
2
1
φ
sin
cos
sin
1
φ
φ
φ
⎞
⎟
⎟
⎠
⎞
⎟
⎟
⎠
CP
CP
= 0.5 mA, f
is the programmed
OL
) and phase
OL
= 400 kHz,
Rev. A | Page 39 of 112
system clock bit in the cal/sync register (Register 0A02, Bit 0).
During the calibration process, the device calibrates the VCO
amplitude and frequency. The status of the system clock cali-
bration process is user accessible via the system clock register
(Register 0D01, Bit 1). It is also available via the IRQ monitor
register (Register 0D02, Bit 1) provided the status bit is enabled
via the IRQ mask register.
When the calibration sequence is complete, the SYSCLK PLL
eventually attains a lock condition, at which point the system
clock stability timer begins its countdown sequence. Expiration
of the timer indicates that the SYSCLK PLL is stable, which is
reflected in the system clock register (Register 0D01, Bit 4).
Note that the monitors/detectors associated with the input
references (REFA/AA – REFD/DD) are internally disabled until
the SYSCLK PLL indicates that it is stable.
CLOCK DISTRIBUTION
The clock distribution block of the AD9548 provides an
integrated solution for generating multiple clock outputs based
on frequency dividing the DPLL output. The distribution
output consists of four channels (OUT0 to OUT3). Each of the
four output channels has a dedicated divider and output driver,
as appears in Figure 47.
Clock Input (CLKINx)
The clock input handles input signals from a variety of logic
families (assuming proper terminations and sufficient voltage
swing). It also handles sine wave input signals such as those
delivered by the DAC reconstruction filter. Its default operating
frequency range is 62.5 MHz to 500 MHz.
CONTROL
4
SYNC
Figure 47. Clock Distribution
Q
0
4
OUT0
OUT1
OUT2
OUT3
ENABLE
SYNC SOURCE
n
4
/MODE
n
OUT0P
OUT0N
CLKINP
CLKINN
OUT_RSET
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
AD9548