AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 97

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address
0A0F
0A10
1
STATUS READBACK (REGISTER 0D00 TO REGISTER 0D19)
All bits in Register 0D00 to Register 0D19 are read only.
Table 130. EEPROM Status
Address
0D00
Table 131. SYSCLK Status
Address
0D01
See Figure 34 for details.
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
[7:5]
[4]
[3:2]
[1]
[0]
Bits
[7:3]
[2]
[1]
[0]
Bit Name
Ref Mon Override DD
Ref Mon Override D
Ref Mon Override CC
Ref Mon Override C
Ref Mon Override BB
Ref Mon Override B
Ref Mon Override AA
Ref Mon Override A
Ref Mon Bypass DD
Ref Mon Bypass D
Ref Mon Bypass CC
Ref Mon Bypass C
Ref Mon Bypass BB
Ref Mon Bypass B
Ref Mon Bypass AA
Ref Mon Bypass A
Bit Name
Unused
Stable
Unused
Cal in progress
Lock detected
Bit Name
Unused
Fault detected
Load in progress
Save in progress
Overrides the reference monitor REF fault signal for Reference DD (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference D (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference CC (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference C (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference BB (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference B (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference AA (default = 0, not
overridden).
Overrides the reference monitor REF fault signal for Reference A (default = 0, not
overridden).
Bypasses the reference monitor for Reference DD (default = 0, not bypassed).
Bypasses the reference monitor for Reference D (default = 0, not bypassed).
Bypasses the reference monitor for Reference CC (default = 0, not bypassed).
Bypasses the reference monitor for Reference C (default = 0, not bypassed).
Bypasses the reference monitor for Reference BB (default = 0, not bypassed).
Bypasses the reference monitor for Reference B (default = 0, not bypassed).
Bypasses the reference monitor for Reference AA (default = 0, not bypassed).
Bypasses the reference monitor for Reference A (default = 0, not bypassed).
Description
Description
The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
The control logic holds this bit set while the system clock calibration is in progress.
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Description
An error occurred while saving data to or loading data from the EEPROM.
The control logic sets this bit while data is being read from the EEPROM.
The control logic sets this bit while data is being written to the EEPROM.
Rev. A | Page 97 of 112
AD9548