AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 87
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD9548/PCBZ
Manufacturer Part Number
AD9548/PCBZ
Description
Clock Generator Evaluation Board
Manufacturer
Analog Devices Inc
Datasheet
1.AD9548BCPZ-REEL7.pdf
(112 pages)
Specifications of AD9548/PCBZ
Silicon Manufacturer
Analog Devices
Application Sub Type
Network Clock Generator/Synchronizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9548
Kit Contents
Board
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9548
Primary Attributes
62.5 ~ 450 MHz Output Frequency
Secondary Attributes
SPI and I2C Compatible Control Port
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 87 of 112
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Table 94. R-Divider—Profile 1
Address
0650
0651
0652
0653
1
Table 95. S-Divider—Profile 1
Address
0654
0655
0656
0657
1
Table 96. Fractional Feedback Divider—Profile 1
Address
0658
0659
065A
Table 97. Lock Detectors—Profile 1
Address
065B
065C
065D
065E
065F
0660
0661
0662
0663
0664 to 067F
Register 0680 to Register 06B1—Profile 2
Table 98. Priorities—Profile 2
Address
0680
The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:4]
[3:2]
[1:0]
[7:6]
[5:0]
Bits
Bits
Bits
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bits
[7]
[6]
[5:3]
[2:0]
U
Phase lock fill rate
Frequency lock fill rate
Bit Name
V
Unused
V
Unused
U
Bit Name
Phase lock threshold
(units determined by
Register 0x0632[7])
Phase lock drain rate
Frequency lock
threshold
(in picoseconds)
Frequency lock drain
rate
Unused
Bit Name
R
Unused
R
Bit Name
S
Unused
S
Bit Name
Phase lock scale
Unused
Promoted priority
Selection priority
1
1
Description
R, Bits[7:0]
R, Bits[15:8]
R, Bits[23:16]
R, Bits[29:24]
Description
S, Bits[7:0]
S, Bits[15:8]
S, Bits[23:16]
S, Bits[29:24]
Description
V, Bits[7:0]
U, Bits[3:0]
V, Bits[9:8]
U, Bits[9:4]
Description
Controls the phase lock threshold unit scaling.
0 = picoseconds.
1 = nanoseconds.
User-assigned priority level (0 to 7) of the reference associated with Profile 2 while
that reference is the active reference. The numeric value of the promoted priority
must be less than or equal to the numeric value of the selection priority.
User-assigned priority level (0 to 7) of the reference associated with Profile 2, which
ranks that reference relative to the others.
Description
Phase lock threshold, Bits[7:0]
Phase lock threshold, Bits[15:8]
Phase lock fill rate, Bits[7:0]
Phase lock drain rate, Bits[7:0]
Frequency lock threshold, Bits[7:0]
Frequency lock threshold, Bits[15:8]
Frequency lock threshold, Bits[23:16]
Frequency lock fill rate, Bits[7:0]
Frequency lock drain rate, Bits[7:0]
Rev. A | Page 87 of 112
AD9548
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