AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 92

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Table 117. Lock Detectors—Profile 3
Address
06DB
06DC
06DD
06DE
06DF
06E0
06E1
06E2
06E3
06E4 to
06FF
Register 0700 to Register 07FF—Profile 4 to Profile 7
Profile 4 (Register 0700 to Register 0731) is identical to Profile 0 (Register 0600 to Register0631).
Profile 5 (Register 0732 to Register 077F) is identical to Profile 1 (Register 0632 to Register 067F).
Profile 6 (Register 0780 to Register 07B1) is identical to Profile 2 (Register 0680 to Register 06B1).
Profile 7 (Register 07B2 to Register 07FF) is identical to Profile 3 (Register 06B2 to Register 06FF).
OPERATIONAL CONTROLS (REGISTER 0A00 TO REGISTER 0A10)
Table 118. General Power-Down
Address
0A00
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reset sans reg map
Unused
SYSCLK power-down
Reference power-
down
TDC power-down
DAC power-down
Dist power-down
Full power-down
Phase lock drain rate
Frequency lock fill rate
Bit Name
Phase lock threshold
(units determined by
Register 0x06B2[7])
Phase lock fill rate
Frequency lock
thresh-old (in
picoseconds)
Frequency lock drain
rate
Unused
Description
Reset internal hardware but retain programmed register values.
0 (default) = normal operation.
1 = reset.
Place SYSCLK input and PLL in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place reference clock inputs in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the time-to-digital converter in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the DAC in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the clock distribution outputs in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the entire device in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Description
Phase lock threshold, Bits[7:0]
Phase lock threshold, Bits[15:8]
Phase lock fill rate, Bits[7:0]
Phase lock drain rate, Bits[7:0]
Frequency lock threshold, Bits[7:0]
Frequency lock threshold, Bits[15:8]
Frequency lock threshold, Bits[23:16]
Frequency lock fill rate, Bits[7:0]
Frequency lock drain rate, Bits[7:0]
Rev. A | Page 92 of 112