AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 46

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Typically, when the AD9548 asserts the IRQ pin, the user
interrogates the IRQ monitor register to identify the source of
the interrupt request. After servicing an indicated interrupt, the
user should clear the associated IRQ monitor register bit via the
IRQ clearing register (Address 0A04 to Address 0A0B). The bits
in the IRQ clearing register have a one-to-one correspondence
with the bits in the IRQ monitor register. Note that the IRQ
clearing register is autoclearing. The IRQ pin remains asserted
until the user clears all of the bits in the IRQ monitor register
that indicate an interrupt.
It is also possible to collectively clear all of the IRQ monitor
register bits by setting the reset all IRQs bit in the reset function
register (Register 0A03, Bit 1). Note that this is an autoclearing
bit. Setting this bit results in deassertion of the IRQ pin.
Alternatively, the user can program any of the multifunction
pins to clear all IRQs. This allows the user to clear all IRQs by
means of a hardware pin rather than by a serial I/O port operation.
WATCHDOG TIMER
The watchdog timer is a general-purpose programmable timer.
To set the timeout period, the user writes to the 16-bit
watchdog timer register (Address 0211 to Address 0212). A
value of 0 in this register disables the timer. A nonzero value
sets the timeout period in milliseconds, giving the watchdog
timer a range of 1 ms to 65.535 sec. The relative accuracy of the
timer is approximately 0.1% with an uncertainty of 0.5 ms.
If enabled, the timer runs continuously and generates a timeout
event whenever the timeout period expires. The user has access
to the watchdog timer status via the IRQ mechanism and the
multifunction pins (M0 to M7). In the case of the multifunction
pins, the timeout event of the watchdog timer is a pulse that
lasts 32 system clock periods.
There are two ways to reset the watchdog timer (thereby
preventing it from causing a timeout event). The first is by
writing a Logic 1 to the autoclearing reset watchdog bit in the
reset function register (Register 0A03, Bit 0). Alternatively, the
user can program any of the multifunction pins to reset the
watchdog timer. This allows the user to reset the timer by
means of a hardware pin rather than by a serial I/O port operation.
Rev. A | Page 46 of 112
EEPROM
EEPROM Overview
The AD9548 contains an integrated 2048-byte, electrically
erasable, programmable read-only memory (EEPROM). The
AD9548 can be configured to perform a download at power-up
via the multifunction pins (M3 to M7), but uploads and down-
loads can also be done on demand via the EEPROM control
register (Address 0E00 to Address 0E03).
The EEPROM provides the ability to upload and download
configuration settings to and from the register map. Figure 49
shows a functional diagram of the EEPROM.
Register 0E10 to Register 0E3F represent a 48-byte scratch pad
that enables the user to store a sequence of instructions for
transferring data to the EEPROM from the device settings
portion of the register map. Note that the default values for
these registers provide a sample sequence for saving/retrieving
all of the AD9548 EEPROM-accessible registers. Figure 49
shows the connectivity between the EEPROM and the controller
that manages data transfer between the EEPROM and the
register map.
The controller oversees the process of transferring EEPROM data
to and from the register map. There are two modes of operation
handled by the controller: saving data to the EEPROM (upload
mode) or retrieving data from the EEPROM (download mode).
In either case, the controller relies on a specific instruction set.
M7
M6
M5
M4
M3
SETTINGS
ADDRESS
POINTER
DEVICE
DEVICE SETTINGS
(0100 TO 0A10)
Figure 49. EEPROM Functional Diagram
REGISTER MAP
CONTROLLER
EEPROM
SCRATCH PAD
(0E10 TO 0E3F)
SCRATCH PAD
ADDRESS
POINTER
ADDRESS
POINTER
EEPROM
DATA
INPUT/OUTPUT
SERIAL
PORT
(000 TO 7FF)
EEPROM