MC33696MOD315EV Freescale Semiconductor, MC33696MOD315EV Datasheet
MC33696MOD315EV
Specifications of MC33696MOD315EV
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MC33696MOD315EV Summary of contents
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... OOK and FSK transmission and reception • 20 kbps maximum data rate using Manchester coding • supply voltage • Programmable via SPI • 6 kHz PLL frequency step © Freescale Semiconductor, Inc., 2006–2010. All rights reserved. LQFP32 RSSIOUT 1 VCC2RF 2 RFIN 3 GNDLNA 4 ...
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... Transmitter: • 7.25 dBm output power • Programmable output power • FSK done by PLL programming Ordering information Temperature Range –40°C to +85°C –20°C to +85°C 2 QFN Package LQFP Package MC33696FCE/R2 MC33696FJE/R2 MC33696FCAE/R2 MC33696FJAE/R2 MC33696 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Freescale Semiconductor MC33696 Data Sheet, Rev. 12 Features 3 ...
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... Digital interface clock I/O Digital interface enable input Digital I/O ground 2 3 5.5 V input No connection Strobe oscillator capacitor or external control input Ground 2 2.7 V power supply for analog modules for decoupling capacitor RF switch control output General ground MC33696 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... ESD HBM voltage capability on each pin ESD MM voltage capability on each pin Solder heat resistance test (10 s) Storage temperature Junction temperature NOTES: 1 Human body model, AEC-Q100-002 rev Machine model, AEC-Q100-003 rev. C. Freescale Semiconductor Table 2. Maximum Ratings Symbol MC33696 Data Sheet, Rev. 12 Maximum Ratings Value V V – ...
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... CC3V V CC5V V CCPA Figure 43 or Figure 44 also possible to use power supply MC33696 Data Sheet, Rev Temperature Range –40°C to +85°C –20°C to +85°C 2.7 to 3.6 2.1 to 3.6 4.5 to 5.5 4.5 to 5.5 3.0 to 3.6 3.0 to 3.6 CCDIG. Freescale Semiconductor Unit ...
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... It is also possible to define two different configurations for the receiver (frequency, data rate, data manager, modulation, etc.) that are automatically loaded during wakeup or under MCU control. If the PLL goes out of lock, received data is ignored. Freescale Semiconductor NOTE MC33696 Data Sheet, Rev. 12 ...
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... MC33696 Data Sheet, Rev. 12 Dataclk F Digclk F dataclk digclk Divider (kHz) Divider (kHz) 60 282.791 30 565.582 60 293.023 30 586.047 80 296.864 40 593.728 80 302.383 40 604.767 80 302.017 40 604.035 80 318.783 40 637.565 and the value ref Freescale Semiconductor T digclk (µs) 1.77 1.71 1.68 1.65 1.66 1.57 ...
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... The interface is operated by six I/O pins. • CONFB — Configuration control input The configuration mode is reached by setting CONFB to low level. 1. Refer to parameter 3.3 found in Section 21.3, “Receiver Parameters.” Freescale Semiconductor /12×1.5/2 Example 1. Cut-off Frequency Computation Registers”). MC33696 Data Sheet, Rev. 12 MCU Interface ...
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... SPI master, data sent on MOSI with clock on SCLK (SEB=0) DME = 0 SPI deselected, received data are directly sent to MOSI (SEB=0) Standby / LVD SPI deselected, all I/O are high impedance (SEB =1) 10 Section 12.3, “Receiver On/Off MC33696 Digital Interface Use MC33696 Data Sheet, Rev. 12 Table 5). Freescale Semiconductor ...
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... At any time, a low level applied to CONFB forces the finite state machine into configuration mode, whatever the current state. This is not always shown in state diagrams, but must always be considered. Refer to (Section 16, “Power-On Reset and MC33696 and configuration mode. Freescale Semiconductor Figure 2 for more details about all the conditions that must digclk Figure 3 ...
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... Receive Mode Receive Mode Receive Mode Receive Mode … and DME = 1 … and DME = 1 … and DME = 1 … and DME = 1 … and SOE = 0 … and SOE = 0 … and SOE = 0 … and SOE = 0 Figure12 Figure12 Figure12 Figure12 See See See See Freescale Semiconductor ...
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... State 5b: The receiver is kept on by the STROBE pin. Raw data is output on the MOSI line. For all states: At any time, a low level applied to CONFB forces the state machine to state 1, configuration mode. Freescale Semiconductor NOTE Figure 3 shows the state diagram. STROBE = 0 State 5 ...
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... Figure 4 shows the state diagram. STROBE = 0 State 0 Off Off Counter = ROFF[2:0] or STROBE = 1 State 0b On Raw Data on MOSI Figure 4. Receive Mode, DME = 0, SOE = 1 MC33696 Data Sheet, Rev. 12 SPI Deselected STROBE = 0 On Counter = RON[3:0] and STROBE different than 1 Freescale Semiconductor ...
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... The MC33696 data manager is able to decode Manchester-coded messages. For other codings, the data manager should be disabled (DME=0) for raw data to be available on MOSI. Freescale Semiconductor Recovered Clock Updated to I ncoming Signal Data Rate Recovered Clock Updated to I ncoming Signal Data Rate ...
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... Figure 7. Example of Frame Format HEADER HEADER MC33696 Data Sheet, Rev. 12 ORIGINAL DATA MANCHESTER CODED DATA DATA ………… DATA ………… EOM EOM Figure 8. The ID field must be greater DATA ………… DATA ………… Freescale Semiconductor ...
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... It is possible to build a tone to form the detection sequence by programming the ID register with a full sequence of ones or zeroes. Once the ID is detected, a HEADER will be searched to detect the beginning of the useful data to send on the SPI port. See Section 12.2.4, “State Machine in Receive Mode When detected when SOE=1 or SOE=0. Freescale Semiconductor Clock Recovery Clock Recovery Manchester 1 Manchester ‘ ...
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... However, external control via the STROBE pin is still possible, and overrides the strobe oscillator command Field ID Field Off Off Off Time Off Time ID ID Detected Detected MC33696 Data Sheet, Rev Header Header Data Data EOM EOM On On Data Data Freescale Semiconductor Off Off ...
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... For all states: At any time, a low level applied to STROBE forces the circuit to state 10, and a low level applied on CONFB forces the state machine to state 1, configuration mode. When an EOM occurs before the current byte is fully shifted out, dummy bits are inserted until the number of shifted bits is a multiple of 8. Freescale Semiconductor MC33696 Data Sheet, Rev. 12 Receive Mode 19 ...
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... ID Detected State 12 On Waiting for a Valid Header Header Received State 13 On Output Data and Clock Waiting for End of Message EOM Received and STROBE ≠ 1 Figure 11. Receive Mode, DME = 1, SOE = 1 MC33696 Data Sheet, Rev. 12 STROBE = 0 STROBE = 1 EOM Received and STROBE = 1 Freescale Semiconductor ...
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... STROBE is high. • State 23: A header or its complement has been received; data and clock signals are output on the SPI port until an EOM indicates the end of the data sequence. If the complement of the header has been Freescale Semiconductor STROBE = 0 State 20 Standby/LVD STROBE = 1 ...
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... Refer to preamble definition found in 22 Off Off Setting Setting Toff Toff Time Time Detected Detected Figure 13. Receiver Usable Window 2 , and setup of all analog parameters Figure 9. MC33696 Data Sheet, Rev Data Data Header Header (AGC and demodulator need some Freescale Semiconductor EOM EOM ...
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... The input signal is measured at two different points in the receiver chain by two different means, as follows. • At the IF filter output, a progressive compression logarithmic amplifier measures the input signal, ranging from the sensitivity level up to –50 dBm. Freescale Semiconductor (see Table 19; begins after the crystal oscillator has started) digclk ...
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... If RSSIE is reset, the whole RSSI module is switched off, reducing the current consumption. The output buffer connected to RSSIOUT is set to high impedance. 24 Register”). LNA AGC Out D1 R1 Σ C1 Figure 15. RSSI Simplified Block Diagram MC33696 Data Sheet, Rev. 12 RSSI Register ADC MSB S2 RSSIOUT Freescale Semiconductor LSB ...
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... The ADC runs continuously, and continually updates the RSSI register. Thus, reading this register gives the most recent conversion value, prior to the register being read. The minimum duration of the high pulse on CONFB is 32 × digclk Freescale Semiconductor digclk . Therefore, the minimum duration of the high pulse on digclk Open ...
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... In FSK modulation (MODU = 1), modulation is performed by switching the RF carrier between two values. MOSI = 0: f corresponding to a logical 0 carrier0 MOSI = 1: f corresponding to a logical 1 carrier1 26 Open Closed Frozen CMD RSSI Data Figure 18. Transfer in Transmit Mode MC33696 Data Sheet, Rev. 12 Updated Frozen CMD RSSI Figure Freescale Semiconductor 18). ...
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... SPI transfers are 8-bit based and always begin with a command byte, which is supplied by the MCU on MOSI considered as a command byte, this byte must come after a falling edge on CONFB. Figure 19 shows the content of the command byte. Freescale Semiconductor 26) and Section 18.3, “Frequency MC33696 Data Sheet, Rev. 12 Standby: LVD Mode Registers,” ...
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... Figure 19. Command Byte Table 7. Number N of Accessed Registers Number N of Accessed Registers Timing,” to view the timing definition for SPI communication. NOTE Interface,” for more details about setting the level on MC33696 Data Sheet, Rev. 12 Bit 2 Bit 1 Bit R/W Table 7. Freescale Semiconductor . digclk ...
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... CONFB, the circuit stays in State 1, the only state in this mode. Figure 22 describe the valid sequence for enabling a correct transition from Standby/LVD mode to configuration mode. SPI startup time corresponds to the addition of the crystal oscillator lock time (parameter 5.10) and the PLL lock time (parameter 5.9). Freescale Semiconductor MC33696 Data Sheet, Rev. 12 ...
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... Along with the ramp-up of power supply, one of these two conditions must be complied with: — Power supply of the MC33696 must rise from — The level on STROBE pin is lower than 0.75 V until the power supply reaches digclk 3 3 Figure NOTE MC33696 Data Sheet, Rev order to reset the state machine 24: Section 10, “MCU Freescale Semiconductor ...
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... MCU. This automatic feature may be used only in receiver mode; however, if one of the register banks is related to a transmitter configuration, it may be accessed directly by programing some bits to define the active bank, thus allowing fast switching between receiver mode and transmitter mode, or between any different possible configurations. Freescale Semiconductor Figure 44 for application schematic in Mode.” ...
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... At any time possible to know which is the active bank by reading the status bit BANKS. Bit Name Direction Location BANKS R A & Location Bank A Bank B Comment Bank status: indicates which register bank is active. This bit, available in Bank A and Bank B, returns the same value. MC33696 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... BANKA = X, BANKB = 0 State A OFF Strobe Pin If strobe pin is 1, configuration is defined by Bank A, BANKS = 1. If strobe pin is 0, MC33696 configuration is OFF message is received during State A, current state remains State end of message. Freescale Semiconductor State A OFF MC33696 Data Sheet, Rev. 12 Configuration Switching 33 ...
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... The MCU can override strobe oscillator control by controlling the strobe pin level. If MCU I/O port is in high impedance, the strobe oscillator will control the OFF/ON state of the MC33696. The various available sequences are described in the following subsections. 34 State B OFF MC33696 Data Sheet, Rev. 12 OFF State A Section 12.3, “Receiver Freescale Semiconductor ...
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... If strobe pin is 1, the state is ON and defined by BANKS at that time. It remains this state up to the release of strobe and end of message if a message is being received. • message is being received during State current state remains State end of message. Freescale Semiconductor State A OFF State B OFF ...
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... SL (Switch Level) selects the active level of the SWITCH output pin. 36 Bit 5 Bit 4 Bit 3 CF1 CF0 RESET R/W R/W R/W Figure 25. CONFIG1 Register LOF1 LOF0 MC33696 Data Sheet, Rev. 12 Bit 2 Bit 1 Bit 0 Addr SL LVDE CLKE $ R/W R/W R/W CF1 CF0 Freescale Semiconductor ...
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... F and FT. MODU (Modulation) sets the data modulation type On/Off Keying (OOK) modulation 1 = Frequency Shift Keying (FSK) modulation DR[1:0] (Data Rate) configure the receiver blocks operating in base band. Freescale Semiconductor Table 9. Active Level of SWITCH Output Pin Transceiver Function Level on SWITCH Receiving ...
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... Bit 5 Bit 4 Bit 3 OLS LVDS ILA1 R/W Figure 27. CONFIG3 Register MC33696 Data Sheet, Rev. 12 Data Manager Data Rate Range 2–2.8 kBd 4–5.6 kBd 8–10.6 kBd 16–22.4 kBd Bit 2 Bit 1 Bit 0 Addr ILA0 OLA1 OLA0 $ R/W R/W R/W Freescale Semiconductor ...
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... If AFFC is set, AFF[1:0] allow the overall receiver sensitivity to be improved by reducing the average filter cut-off frequency. The typical preamble duration of three Manchester zeroes or ones at the data rate must then be increased, as shown in Freescale Semiconductor Table 11. RF Input Level Attenuation RF Input Level ILA0 ...
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... RAGC (Reset Automatic Gain Control) resets both receiver internal AGCs action 40 versus DR[1:0] and AFF[1:0] DR[1: — — — 10 — — — 11 Bit 5 Bit 4 Bit 3 MODE RSSIE EDD R/W R/W R/W Figure 28. COMMAND Register MC33696 Data Sheet, Rev Bit 2 Bit 1 Bit 0 RAGC FAGC BANKS R/W R/W R Freescale Semiconductor Addr $03 ...
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... R/W Bit 15 Bit 14 Bit Name FTA3 FTA2 Reset Value 0 0 Access R/W R/W Bit 7 Bit 6 Bit Name FTB7 FTB6 Reset Value 0 0 Access R/W R/W Freescale Semiconductor Bit 13 Bit 12 Bit 11 FSK1 FSK0 F11 R/W R/W R/W Bit 5 Bit 4 Bit R/W R/W R/W Figure 29 ...
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... F x(FSK[3:0]+1)/ 1024 ref Frequency Deviation Δf ± 12 kHz 0000 ± 24 kHz 0001 ± 36 kHz 0010 ... ... ± 192 kHz 1111 carrier to transmit a logical 0 carrier0 to transmit a logical 1 carrier1 MC33696 Data Sheet, Rev (with F = intermediate frequency Table 15. Freescale Semiconductor . The carrier ...
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... BANKA defines the register bank selected, as described in RON[3:0] (Receiver On) define the receiver on time (after crystal oscillator startup) as described in Section 12.3, “Receiver On/Off RON[3:0] ROFF[2:0] (Receiver Off) define the receiver off time as described in Control.” Freescale Semiconductor Frequency Register Value (2 x F/F -35) x 2048 ref (F/F ...
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... R/W R/W R/W Figure 33. HEADER Register MC33696 Data Sheet, Rev. 12 Strobe Bit 2 Bit 1 Bit 0 ID2 ID1 ID0 R/W R/W R/W Table 21. 2 bits 4 bits 5 bits 6 bits Bit 2 Bit 1 Bit 0 HD2 HD1 HD0 R/W R/W R/W Table 22. Freescale Semiconductor Addr $0A Addr $0B ...
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... Bit can be read. Read or write resets the value. R [A] Bit can be read. This returns the same value as Bank A. RR [A] Bit can be read. This returns the same value as Bank A. Read or write resets the value. Freescale Semiconductor Table 22. Header Length Selection HDL1 HDL0 HD Length ...
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... Read or write from any bank resets value. R/W-R[A} SOE can be modified in BANKA. Access from BANKB reflects BANKA value. R-R[A} RSSI value is directly read from RSSI converter. Reflected value is the same whatever the active byte. MC33696 Data Sheet, Rev. 12 Comment Freescale Semiconductor ...
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CONFIG1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Name LOF1 LOF0 CF1 CF0 RESET Reset Value R/W R/W R/W R/W R 304–434 304–315 315–434 314 No ...
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FT1-A 700701 h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Name FTA11 FTA10 FTA9 FTA8 FTA7 Reset Value R/W R/W R/W R/W R/W 07h FT2 Bit 7 Bit ...
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... Format.” 2 Depending on the PLL status before entering configuration mode. For example, the transition time from standby to receiver running (FSK modulation, 19.2 kBd, AFFC = 0, data manager enabled) is: 0 µ 1)/19.2k = 970 µs. Freescale Semiconductor Table 24. Transition Time Definition Crystal Oscillator PLL Timing Startup Time, Parameter 5 ...
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... V –0.1 — CC — 0.7 x — V CCDIG 1.4 1.6 1.8 2.4 — — Limits Max Max Typ (FCE, (FCAE, FJE) FJAE) — –104 –99 –97 Freescale Semiconductor Unit mA μ μA μ Unit dBm ...
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... Out-of-band jammer Sensitivity reduced by 3dB desensitization CW jammer at F 2.12 Sensitivity reduced by 3dB CW jammer at F 2.13 RFIN parallel resistance Receive mode Freescale Semiconductor Table 3. Values refer to the circuit recommended in the application Figure 51, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect = 25° ...
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... MHz 25°C Temperature (°C) MC33696 Data Sheet, Rev. 12 Limits Max Max Typ (FCE, (FCAE, FJE) FJAE) — — — — 1.2 — — — — — — — — — — — — 85°C Freescale Semiconductor Unit Ω pF dBm dBm dB dB ...
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... Figure 38. FSK Sensitivity Variation Versus Temperature Freescale Semiconductor OOK Sensitivity Variation vs Voltage (Ref : 3V, 25°C, 4800bps) 2 Voltage (V) FSK Sensitivity Variation vs Temperature (Ref : 3V, 25°C, +/-64kHz, 4800 bps ) 315 MHz 434 MHz 868 MHz 916 MHz 25° ...
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... FSK Sensitivity Variation vs Voltage (Ref : 3V, 25°C, +/-64kHz, 4800bps ) 315 MHz 434 MHz 868 MHz 916 MHz 2 Voltage (V) Sensitivity Variation Versus Data Rate (Ref : 25°C, 3V, 434MHz , OOK, 4800bps) 4800 9600 Data Rate (bps) MC33696 Data Sheet, Rev. 12 3.6 V 19200 Freescale Semiconductor ...
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... Figure 41. FSK Sensitivity Variation Versus Data Rate Freescale Semiconductor Sensitivity Variation vs Data Rate (Ref : 25°C, 3V, 434MHz , FSK +/-64kHz, 4800bps) 4800 9600 Data Rate (bps) MC33696 Data Sheet, Rev. 12 Electrical Characteristics 19200 55 ...
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... FAGC = 0, input signal from –50 dBm to –100 dBm MC33696 Data Sheet, Rev. 12 120 130 140 150 160 170 Limits Min Typ Max — 1.5 — — 380 — — — 1.387 1.635 — — — 15 — Freescale Semiconductor Unit MHz kHz MHz MHz ms ...
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... Digital RSSI Registers for Input signal @–24 dBm 21.4 Transmitter: RF Parameters RF parameters assume a matching network between test equipment and the D.U.T, and apply to all bands unless otherwise specified. Freescale Semiconductor Table 3. Values refer to the circuit recommended in the application through Figure 54), unless otherwise specified ...
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... Freescale Semiconductor ...
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... Figure 43. Output Power Versus Temperature Freescale Semiconductor Table 3. Values refer to the circuit recommended in the application Test Conditions Min Comments (FCE, FJE) OLA[1:0] = 00, TX mode — OLA[1:0] = 00, TX mode — OLA[1:0] = 00, TX mode — ...
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... MHz 916 MHz 3 V 3.6 V Limits Min Typ Max — 50 100 — 30 — — 58 — — 248 — — 160 — — 278 — — 0.6 1.2 — — 120 Freescale Semiconductor Unit μs μs kHz kHz kHz kHz ms Ω ...
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... Figure measurement 3 25° Parameter 6.1 Period range 6.2 External capacitor C3 6.3 Sourced/sink current 6.4 High threshold voltage 6.5 Low threshold voltage 6.6 Overall timing accuracy Freescale Semiconductor Reference & Type 315 MHz 434 MHz LN-G102-1182 NX5032GA NDK NDK 17.5814 24.19066 ...
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... V CCDIG2 — — CCDIG2 — — CCDIG2 1 — 100 0.5 — 10 (see Section 5, “Power Supply”). Section 5, “Power Limits Min Typ Max — — 0 CCIO — — CCIO — 80 150 = 3V) — — 0 — — CC Freescale Semiconductor Unit Supply”). Unit ...
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... In this case and for a practical use, the pulse required on CONFB between accesses must be higher than 100 ns only if STROBE signal is always set to high level. Freescale Semiconductor Table 3. Values refer to the circuit recommended in the application ...
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... Note: The external pullup resistor set on SEB pin (R2) is not mandatory. Instead of R2, an external pulldown resistor may be connected between SEB pin and ground. 22.1 Receiver Schematics Figure 43 and Figure 44 show the application schematic in receive mode for 3 V operation. 64 9.4 9.9 MC33696 Data Sheet, Rev. 12 9.5 Freescale Semiconductor ...
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... Receiver Schematics Operation—MCU Controls Wakeup C1 100nF VCC2 L1 C2 1nF C3 C4 VCC2 C5 100pF Figure 47. MC33696 Application Schematic (3 V) The ON/OFF sequencing in receive mode is controlled by driving a low or high level by the MCU on STROBE pin. Freescale Semiconductor VCC 26 C12 100pF VCC2 C11 34 100nF SWITCH 1 24 RSSIOUT SEB 2 ...
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... MISO U1 5 VCC2VCO CONFB MC33696 6 GNDPA1 DATACLK 7 RFOUT RSSIC 8 GNDPA2 GNDDIG VCC C7 1nF VCC2 X4 C10 100nF 470k 1% 100 nF 100nF C6 6.8pF MC33696 Data Sheet, Rev. 12 RSSIOUT STROBE 3V GND VCC VCC R2 R3 10k 10k 24 SEB 23 SCLK 22 MOSI 21 MISO 20 CONFB 19 DATACLK 18 RSSIC 17 Freescale Semiconductor ...
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... Wakeup C1 100nF VCC2 L1 C2 1nF C3 C4 VCC2 C5 100pF Figure 49. MC33696 Application Schematic (5 V) The ON/OFF sequencing in receive mode is controlled by driving a low or high level by the MCU on STROBE pin. Freescale Semiconductor VCC C12 100pF VCC2 C11 100nF SWITCH 1 24 RSSIOUT SEB 2 23 VCC2RF ...
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... DATACLK 7 RFOUT RSSIC 8 GNDPA2 GNDDIG C7 1nF VCC2 X5 C10 100nF 470k 1% 100 nF 100nF C6 6.8pF MC33696 Data Sheet, Rev RSSIOUT 14 STROBE GND VCC VCC R2 R3 10k 10k 24 16 SEB 23 20 SCLK 22 18 MOSI 21 21 MISO 20 19 CONFB 19 17 DATACLK 18 22 RSSIC 17 Freescale Semiconductor ...
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... Figure 51 shows the application schematic in transmit mode for 3 V operation. VCC C13 C1 100nF 100nF C14 100pF C2 100pF 1nF C3 C4 Figure 51. MC33696MC33596 Application Schematic ( Transmit Mode Only Freescale Semiconductor VCC C12 1 00pF VCC2 C11 100nF SWITCH 1 RSSIOUT SEB VCC2 2 VCC2RF SCLK 3 RFIN ...
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... SEB SEB SEB SEB SCLK SCLK SCLK SCLK MOSI MOSI MOSI MOSI MISO MISO MISO MISO CONFB CONFB CONFB CONFB DATACLK DATACLK DATACLK DATACLK RSSIC RSSIC RSSIC RSSIC 17 17 GNDDIG GNDDIG VCC VCC R1 R1 470k 1% 470k 1% Freescale Semiconductor ...
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... C14 100pF L15 C15 L1 1nF C5 1nF C3 C4 Figure 53. MC33696 Application Schematic ( Transceiver Mode The ON/OFF sequencing for the receiver is controlled by driving a low or high level by the MCU on STROBE pin. Freescale Semiconductor VCC C12 100pF VCC2 C11 100nF SWITCH C1 1 RSSIOUT 100nF VCC2 ...
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... SEB SEB SEB SEB SCLK SCLK SCLK SCLK MOSI MOSI MOSI MOSI MISO MISO MISO MISO CONFB CONFB CONFB CONFB DAT ACLK DAT ACLK DATACLK DATACLK RSSIC RSSIC RSSIC RSSIC 17 17 GNDDIG GNDDIG VCC VCC R1 R1 470k 1% 470k 1% Freescale Semiconductor ...
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... MC33696 RF Modules available for MC33696 evaluation. Matching networks should be retuned if any change is made to the PCB (track width, length or place, or PCB thickness, or component value). Never use, as is, a matching network designed for another PCB. Freescale Semiconductor NOTE MC33696 Data Sheet, Rev. 12 PCB Design Recommendations ...
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... Case Outline Dimensions 24 Case Outline Dimensions 24.1 LQFP32 Case 74 MC33696 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Freescale Semiconductor MC33696 Data Sheet, Rev. 12 Case Outline Dimensions 75 ...
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... Case Outline Dimensions 76 MC33696 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... QFN32 Case Freescale Semiconductor MC33696 Data Sheet, Rev. 12 Case Outline Dimensions 77 ...
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... Case Outline Dimensions 78 MC33696 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Freescale Semiconductor MC33696 Data Sheet, Rev. 12 Case Outline Dimensions 79 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...