ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 10

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
Delay Line DMA
The ADSP-21469 processor provides delay line DMA function-
ality. This allows processor reads and writes to external delay
line buffers (and hence to external memory) with limited core
interaction.
Scatter/Gather DMA
The ADSP-21469 processor provides scatter/gather DMA func-
tionality. This allows processor DMA reads/writes to/from non-
contiguous memory blocks.
Table 7. DMA Channels
1
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
FFT Accelerator
FFT accelerator implements radix-2 complex/real input, com-
plex output FFT with no core intervention. The FFT accelerator
runs at the peripheral clock frequency.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-21469 boots at system
power-up from an 8-bit EPROM via the external port, link port,
an SPI master, or an SPI slave. Booting is determined by the
boot configuration (BOOTCFG2–0) pins in
Peripheral
SPORTs
IDP/PDAP
SPI
UART
External Port
Link Port
Accelerators
Memory-to-Memory
MLB
Automotive models only.
1
DMA Channels
16
8
2
2
2
2
2
2
31
Table
8.
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Table 8. Boot Mode Selection
The Running Reset feature allows a user to perform a reset of
the processor core and peripherals, without resetting the PLL
and DDR2 DRAM controller or performing a Boot. The func-
tionality of the RESETOUT pin also acts as the input for
initiating a Running Reset. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
Power Supplies
The processors have separate power supply connections
for the internal (V
(V
meet the V
the V
nected to the same power supply.
Note that the analog supply pin (V
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
V
the V
recommended ferrite chip is the muRata BLM18AG102SN1D).
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
traces to connect the bypass capacitors to the analog power
(V
AGND pins specified in
not the analog ground plane on the board—the AGND pin
should connect directly to digital ground (GND) at the chip.
BOOTCFG2–0
000
001
010
011
100
101
DD_A
V DD_INT
DD_A
DD_A
DD_EXT
DD_A
pin. Place the filter components as close as possible to
) power supplies. The internal and analog supplies must
) and ground (AGND) pins. Note that the V
/AGND pins. For an example circuit, see
DD_INT
HI Z FERRITE
BEAD CHIP
specification. All external supply pins must be con-
Figure 3. Analog Power (V
DD_INT
specifications. The external supply must meet
LOCATE ALL COMPONENTS
CLOSE TO VDD_A AND AGND PINS
Booting Mode
SPI Slave Boot
SPI Master Boot
AMI Boot (for 8-bit Flash boot)
No boot occurs, processor executes from
internal ROM after reset
Link Port 0 Boot
Reserved
Figure 3
100nF
), external (V
DD_INT
are inputs to the processor and
10nF
DD_A
DD_A
DD_EXT
and GND. Use wide
) Filter Circuit
) powers the processor’s
1nF
), and analog
Figure
DD_A
ADSP-2146x
VDD_A
AGND
and
3. (A