ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 50

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 47. S/PDIF Transmitter Input Data Timing
1
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 48. Oversampling Clock (HFCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
HFCLK Frequency for HFCLK = 384 × Frame Sync
HFCLK Frequency for HFCLK = 256 × Frame Sync
Frame Rate (Fs)
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
SISFS
SIHFS
SISD
SIHD
SITXCLKW
SITXCLK
SISCLKW
SISCLK
be either CLKIN or any of the DAI pins.
Table
1
1
1
1
47. Input signals are routed to the DAI_P20–1 pins
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Transmit Clock Width
Transmit Clock Period
Clock Width
Clock Period
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(TxCLK)
(SCLK)
(FS)
t
SITXCLKW
Figure 36. S/PDIF Transmitter Input Timing
Rev. 0 | Page 50 of 72 | June 2010
t
SISCLKW
SAMPLE EDGE
t
SISFS
t
SISD
t
SISCLK
t
SITXCLK
Max
Oversampling Ratio × Frame Sync <= 1/t
49.2
192.0
Min
3
3
3
3
9
20
36
80
t
t
SIHFS
SIHD
Max
SIHFCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
kHz