ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 48

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left-justified, I
20, or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 33
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed minimum in
24-bit output mode or maximum in 16-bit output mode from
an LRCLK transition, so that when there are 64 serial clock peri-
ods per LRCLK period, the LSB of the data will be right-justified
to the next LRCLK transition.
Table 44. S/PDIF Transmitter Right-Justified Mode
Table 45. S/PDIF Transmitter I
Parameter
Timing Requirement
t
Parameter
Timing Requirement
t
RJD
I
2
SD
shows the right-justified mode. LRCLK is high for the
2
S, or right-justified with word widths of 16, 18,
DAI_P20–1
DAI_P20–1
DAI_P20–1
LRCLK
SDATA
SCLK
DAI_P20–1
DAI_P20–1
DAI_P20–1
LRCLK
SDATA
SCLK
LRCLK to MSB Delay in Right-Justified Mode
LRCLK to MSB Delay in I
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
LSB
2
S Mode
t
I2SD
MSB
t
RJD
MSB–1
2
S Mode
Rev. 0 | Page 48 of 72 | June 2010
Figure 33. Right-Justified Mode
MSB–2
Figure 34. I
2
S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB+2
LEFT/RIGHT CHANNEL
Figure 34
for the left channel and HI for the right channel. Data is valid on
the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a delay.
Figure 35
left channel and LO for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no delay.
MSB–1
LSB+1
MSB–2
shows the default I
shows the left-justified mode. LRCLK is high for the
LSB
Nominal
16
14
12
8
Nominal
1
LSB+2
2
S-justified mode. LRCLK is low
LSB+1
LSB
Unit
SCLK
SCLK
SCLK
SCLK
Unit
SCLK