ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 33

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AMI Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 30. Memory Read
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
RHC = (number of Read Hold Cycles specified in AMICTLx register) × t
IC = (number of idle cycles specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) × t
Data delay/setup: System must meet t
The falling edge of AMI_MSx, is referenced.
Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
Data hold: User must meet t
AMI_ACK delay/setup: User must meet t
DAD
DRLD
SDS
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
Where PREDIS = 0
Where PREDIS = 1
HI = RHC + Max(IC, (4 × t
HI = RHC + (3 × tDDR2_CLK): Read to Read from same bank
HI = RHC + Max(IC, (3 × t
HI = RHC: Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × t
Address, Selects Delay to Data Valid
AMI_RD Low to Data Valid
Data Setup to AMI_RD High
Data Hold from AMI_RD High
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_RD Low
Address Selects Hold After AMI_RD High
Address Selects to AMI_RD Low
AMI_RD Pulse Width
AMI_RD High to AMI_RD Low
HDRH
DDR2_CLK
DDR2_CLK
in asynchronous access mode. See
DDR2_CLK
DAD
, t
DAAK
DRLD
)): Read to Write from same or different bank
)): Read to Read from different bank
)): Read to Write from same or different bank
, or t
, or t
DSAK
SDS.
1
, for deassertion of AMI_ACK (low).
3, 4
2
4
Rev. 0 | Page 33 of 72 | June 2010
1, 2
2, 5
Test Conditions on Page 58
DDR2_CLK
DDR
DDR2_CLK
2_
CLK
.
Min
2.5
0
RH + 0.20
t
W – 1.4
HI + t
DDR
DDR
2_
2_
CLK
DDR
CLK
– 3.8
2_
CLK
for the calculation of hold times given capacitive and dc loads.
– 1
Max
W + t
W – 3.2
t
W – 7.0
DDR
2_
CLK
DDR
2_
–9.5 + W
CLK
–5.4
ADSP-21469
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns