ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 45 on Page 58
ence levels.
In the following sections, Switching Characteristics specify how
the processor changes its signals. Circuitry external to the pro-
cessor must be designed for compatibility with these signal
characteristics. Switching characteristics describe what the pro-
cessor will do in a given circumstance. Use switching
characteristics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
In the following sections, Timing Requirements apply to signals
that are controlled by circuitry external to the processor, such as
the data input for a read operation. Timing requirements guar-
antee that the processor operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
The VCO frequency is calculated as follows:
f
f
where:
f
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
VCO
VCO
CCLK
VCO
• The product of CLKIN and PLLM must never exceed 1/2 of
• The product of CLKIN and PLLM must never exceed
Figure
f
(INDIV = 0).
f
(INDIV = 1).
= 2
= VCO output
specified in
VCO
VCO
= (2
×
(max) in
(max) in
×
5). This PLL-based clocking minimizes the skew
PLLM
PLLM
Table
×
Table 18
Table 18
×
f
INPUT
under
f
INPUT
18.
)
Test Conditions
if the input divider is not enabled
if the input divider is enabled
÷
(PLLD)
for voltage refer-
Rev. 0 | Page 21 of 72 | June 2010
PLLD = Divider value 2, 4, 8, or 16 based on the PLLD value
programmed on the PMCTL register. During reset this value
is 2.
f
f
f
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table
peripherals are defined in relation to t
specific section for each peripheral’s timing information.
Table 16. Clock Periods
Figure 5
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.
INPUT
INPUT
INPUT
Timing
Requirements
t
t
t
CK
CCLK
PCLK
16. All of the timing specifications for the ADSP-21469
= input frequency to the PLL
= CLKIN when the input divider is disabled, or
= CLKIN  2 when the input divider is enabled
shows core to CLKIN relationships with external oscil-
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t
PCLK
. See the peripheral
ADSP-21469
CCLK