ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 53

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Interface—Slave
Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSOE
DSDHI
DSDHI
DDSPIDS
HDSPIDS
DSOV
Interface Port” chapter.
1
1
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(CP = 0,
(INPUT)
SPICLK
(INPUT)
(INPUT)
(INPUT)
CP = 1)
SPIDS
MISO
MOSI
MISO
MOSI
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
t
t
t
SDSCO
DSOE
DSOV
t
t
SPICHS
SSPIDS
t
DDSPIDS
Rev. 0 | Page 53 of 72 | June 2010
t
DDSPIDS
Figure 39. SPI Slave Timing
t
SPICLS
t
SSPIDS
t
DDSPIDS
t
SPICLKS
t
HDSPIDS
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
0
0
2 × t
t
SSPIDS
t
HSPIDS
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
t
– 2
– 2
– 2
HSPIDS
t
HDS
Max
6.8
8
10.5
10.5
9.5
5 × t
t
SDPPW
ADSP-21469
PCLK
t
t
t
DSDHI
HDSPIDS
DSDHI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns