ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 24

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
Clock Input
Table 18. Clock Input
1
2
3
4
5
6
7
8
Clock Signals
The ADSP-21469 can use an external clock or a crystal. See the
CLKIN pin description in
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL.
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN
achieves a clock speed of 400 MHz).
To achieve the full core clock rate, programs need to configure
the multiplier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
f
t
Applies to all 400 MHz models. See
Applies to all 450 MHz models. See
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
Guaranteed by simulation but not tested on silicon.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
See
Actual input jitter should be combined with ac specifications for accurate timing analysis.
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CK
CKL
CKH
CKRF
CCLK
VCO
CKJ
7, 8
6
Figure 5 on Page 22
5
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
CLKIN Jitter Tolerance
CLKIN
for VCO diagram.
Table
Ordering Guide on Page
Ordering Guide on Page
9. Programs can configure the
t
CKH
Figure 8
70.
70.
Rev. 0 | Page 24 of 72 | June 2010
t
CK
shows the
t
CKL
Figure 7. Clock Input
Min
15
7.5
7.5
2.5
200
–250
3
C1
22pF
400 MHz
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
CCLK
CLKIN
Fundamental Mode Crystal Operation
Figure 8. Recommended Circuit for
.
Max
100
45
45
3
10
900
+250
4
*TYPICAL VALUES
1
25.000 MHz
t
CKJ
R1
1M: *
Y1
ADSP-2146x
Min
13.26
6.63
6.63
2.22
200
–250
XTAL
R2
47: *
C2
22pF
450 MHz
Max
100
45
45
3
10
900
+250
4
2
Unit
ns
ns
ns
ns
ns
MHz
ps