ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 108

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
LIN HARDWARE INTERFACE
LIN Frame Protocol
The LIN frame protocol is divided into four main categories:
break symbol, sync byte, protected identifier, and data bytes.
The format of the frame header, break, synchronization byte,
and protected identifier is shown in Figure 41. Essentially, the
embedded UART, LIN hardware synchronization logic, and the
high voltage transceiver interface all combine on-chip to support
and manage LIN-based transmissions and receptions.
LIN Frame Break Symbol
As shown in Figure 42, the LIN break symbol is used to signal
the start of a new frame. It lasts at least 13 bit-periods, and
a slave must be able to detect a break symbol, even if it expects
data or is in the process of receiving data. The ADuC7032-8L
accomplishes this by using the LHSVAL1 break condition and
break error-detect functionality. The break period does not
need to be accurately measured, but if a bus fault condition
(bus held low) occurs, it must be flagged.
LIN Frame Synchronization Byte
The baud rate of the communication via LIN is calculated from
the sync byte, as shown in Figure 43. The time between the first
falling edge of the sync field and the fifth falling edge of the sync
field is measured. The result is divided by 8 to give the baud
rate of the data that is to be transmitted. The ADuC7032-8L
implements the timing of this sync byte in hardware.
LIN Frame Protected Identifier
After receiving the LIN sync field, the required baud rate for
the UART is calculated. The UART is then configured, allowing
the ADuC7032-8L to receive the protected identifier, as shown
in Figure 44. The protected identifier consists of two sub-fields:
the identifier and the identifier parity. The 6-bit identifier
contains the identifier of the target for the frame. The identifier
signifies the number of data bytes to be either received or
transmitted.
The number of bytes is user-configurable at system level design.
The parity is calculated on the identifier and is dependent on
the revision of LIN for which the system is designed.
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LIN Frame Data Byte
The data byte frame carries between one byte and eight bytes of
data. The number of bytes contained in the frame is dependent
on the LIN master. The data byte frame is split into data bytes,
as shown in Figure 45.
LIN Frame Data Transmission and Reception
When the break symbol and synchronization bytes have been
correctly received, data is transmitted and received via the
COMTX and COMRX MMRs, after configuration of the UART
to the required baud rate.
Configuring the UART for use with LIN requires the use of the
following UART MMRs:
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•
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The required values for COMDIV0, COMDIV1 and COMDIV2
are derived from the LHSVAL0, to generate the required baud rate.
COMCON0 is a line control register. When the UART is
correctly configured, the LIN protocol for receiving and
transmitting data is identical to the UART specification.
Managing data on the LIN bus requires the use of the following
UART MMRs:
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•
•
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Transmitting data on the LIN bus requires that the relevant data
be placed into COMTX. Reading data received on the LIN bus
requires the monitoring of COMRX. To ensure that data is
received or transmitted correctly, COMSTA0 is monitored.
For more information, see the UART Serial Interface section.
Under software control, it is possible to multiplex the UART
data lines (TxD and RxD) to external GPIO pins (GPIO_7 and
GPIO_8). For more information, see the description of the
GPIO Port1 Control Register (GP1CON).
COMDIV0: divisor latch (low byte)
COMDIV1: divisor latch (high byte)
COMDIV2: 16-bit fractional baud divide register
COMTX: 8-bit transmit register
COMRX: 8-bit receive register
COMCON0: line control register
COMSTA0: line status register