ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 7

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Parameter
LIN I/O GENERAL
LIN v.1.3 SPECIFICATION
LIN 2.0 SPECIFICATION
Symmetry of Receive
Baud Rate
VDD
Input Capacitance
LIN Comparator Response
I
I
I
I
V
V
V
V
V
V
V
VBAT Shift
GND Shift
R
V
Transmit Propagation Delay
Symmetry of Transmit
t
D1
D2
LIN DOM MAX
LIN_PAS_REC
LIN_PAS_DOM
LIN_NO_GND
SYM
dV
dV
LIN_DOM
LIN_REC
LIN_CNT
HYS
LIN_DOM_DRV_LOSUP
LIN_DOM_DRV_HISUP
LIN_RECESSIVE
SLAVE
SERIAL DIODE
dt
dt
Time
R
R
R
R
Propagation Delay
Receive Propagation Delay
Propagation Delay
1
1
L
L
L
L
1
1
500 Ω
1000 Ω
500 Ω
1000 Ω
1
1
1
1
30
1
30
30
30
1
1
1
1
1
1
Test Conditions/Comments
Supply voltage range at which the LIN interface is functional
Using 22 Ω resistor
Current limit for driver when LIN bus is in dominant state;
VBAT = VBAT(MAX)
Driver off; 7.0 V < V
Input leakage V
Control unit disconnected from ground,
GND = VDD; 0 V < V
LIN receiver dominant state, VDD > 7.0 V
LIN receiver recessive state, VDD > 7.0 V
LIN receiver center voltage, VDD > 7.0 V
LIN receiver hysteresis voltage
LIN dominant output voltage; VDD = 7.0 V
LIN dominant output voltage; VDD = 18 V
LIN recessive output voltage
Slave termination resistance
Voltage drop at the serial diode, D
V
Bus load conditions (C
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
V
V
V
Bus load conditions (C
1 nF||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω
Slew rate
Slew rate
Bus load conditions ( C
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
Duty Cycle 1
Duty Cycle 2
DDMIN
DDMIN
DDMIN
DDMIN
TH
TH
V
D1 = t
TH
TH
V
D2 = t
Dominant and recessive edges, VBAT = 18 V
Dominant and recessive edges, VBAT = 7 V
Symmetry of rising and falling edge, VBAT = 18 V
Symmetry of rising and falling edge, VBAT = 7 V
SUP
SUP
REC(MAX)
DOM(MAX)
REC(MIN)
DOM(MIN)
= 7 V
= 7 V
= 7 V
= 7 V
= 7.0 V…18 V; t
= 7.0 V…18 V; t
BUS_REC(MIN)
BUS_REC(MAX)
= 0.284 × VBAT,
= 0.744 × VBAT,
= 0.422 × VBAT,
= 0.581 × VBAT,
LIN
/(2 × t
= 0 V
/(2 × t
BUS
LIN
< 18 V; VDD = V
< 18 V; VBAT = 12 V
BUS
BUS
BIT
BIT
BUS
BIT
BIT
||R
||R
= 50 μs,
= 50 μs,
||R
)
)
BUS
BUS
BUS
):
):
):
Rev. A | Page 7 of 120
Ser_Int
LIN
− 0.7 V
Min
1000
7
40
−20
−1
−1
0.6 VDD
0.475 VDD
0.6
0.8
0.8 VDD
0
0
20
0.4
−2
−2
1
0.5
−5
−4
0.396
Typ
5.5
38
0.5 VDD
29
0.7
2
ADuC7032-8L
Max
20,000
18
90
200
+20
+1
0.4 VDD
0.525 VDD
0.175 VDD
1.2
2
0.1 VDD
0.1 VDD
47
1
4
+2
6
+2
3
3
+5
+4
0.581
V
V/μs
Unit
Bits/sec
V
pF
μs
mA
μA
mA
mA
V
V
V
V
V
V
V
V
V
V
kΩ
V
μs
μs
μs
μs
V/μs
μs
μs