ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 69

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TIMERS
The ADuC7032-8L features four general-purpose
timers/counters.
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•
•
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The four timers in their normal mode of operation can be in
either free running mode or periodic mode.
Timers are started by writing data to the control register of the
corresponding timer (TxCON). The counting mode and speed
depend on the configuration chosen in TxCON.
In normal mode, an IRQ is generated each time the value of
the counter reaches 0 when counting down, or each time the
counter value reaches full scale when counting up. An IRQ
can be cleared by writing any value to clear the register of
that particular timer (TxCLRI).
The three timers in their normal mode of operation can be
either free-running or periodic.
Table 53. Timer Event Capture
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Timer0, or lifetime timer
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Description
Timer0.
Timer1.
Timer2 or Wake-Up Timer.
Timer3 or Watchdog Timer.
Reserved.
LIN Hardware.
Flash/EE Interrupt.
PLL Lock.
ADC.
UART.
SPI Master.
XIRQ0 (GPIO IRQ 0).
XIRQ1 (GPIO IRQ 1).
Reserved.
IRQ3 High Voltage IRQ.
SPI Slave.
XIRQ4 (GPIO IRQ 4).
XIRQ5 (GPIO IRQ 5).
Comments
See the Timer0—Lifetime Timer section.
See the Timer1 section.
See the Timer2—Wake-Up Timer section.
See the Timer3—Watchdog Timer section.
Should be written as 0.
See the LIN (Local Interconnect Network) Interface section.
See the Flash/EE Control Interface section.
See the ADUC7032-8L System Clocks section.
See the 16-Bit, Sigma-Delta Analog-to-Digital Converters section.
See the UART Serial Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
Should be written as 0.
See the High Voltage Peripheral Control Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
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In free-running mode, starting with the value in the TxLD
register, the counter decrements/increments from the maximum/
minimum value until zero/full scale and starts again at the
maximum/minimum value. This means that, in free-running
mode, TxVAL is not reloaded when the relevant interrupt bit is
set but the count simply rolls over as the counter underflows or
overflows.
In periodic mode, the counter decrements/increments from
the value in the load register (TxLD MMR) until zero/full scale
starts again from this value. This means when the relevant
interrupt bit is set, TxVAL is reloaded with TxLD and counting
starts again from this value.
Loading the TxLD register with zero is not recommended. The
value of a counter can be read at any time by accessing its value
register (TxVAL).
In addition, Timer0 and Timer1 each has a capture register
(T0CAP and T1CAP, respectively) that can hold the value
captured by an enabled IRQ event. The IRQ events are
described in Table 53.
ADuC7032-8L