ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 79

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ADUC7032BSTZ-88-RL

Manufacturer Part Number
ADUC7032BSTZ-88-RL
Description
Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7032BSTZ-88-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7032BSTZ-88-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADUC7032BSTZ-88-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
GENERAL-PURPOSE I/O
The ADuC7032-8L features nine general-purpose bidirectional
I/O pins (GPIO). In general, many of the GPIO pins have multiple
functions that can be configured by user code. By default, the
GPIO pins are configured in GPIO mode. All GPIO pins have
an internal pull-up resistor, their sink capability is 0.8 mA, and
they can source 0.1 mA.
The nine GPIOs are grouped into three ports: Port0, Port1, and
Port2. Port0 is five bits wide. Port1 and Port2 are both two bits
wide. The GPIO assignment within each port is shown in Table 58.
A typical GPIO structure is shown in Figure 36.
External interrupts are present on GPIO_0, GPIO_5, GPIO_7,
and GPIO_8. These interrupts are level triggered and are active
high. These interrupts are not latched; therefore, the interrupts
source must be present until either IRQSTA or FIQSTA is
interrogated.
OUTPUT DRIVE ENABLE
1
ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8.
GPxDAT[31:24]
GPxDAT[23:16]
OUTPUT DATA
GPxDAT[7:0]
INPUT DATA
GPIO IRQ
Figure 36. ADuC7032-8L GPIO
Rev. A | Page 79 of 120
1
The interrupt source must be active for at least one CD-divided
core clock to guarantee recognition.
All port pins are configured and controlled by four sets (one set
for each port) of four port-specific MMRs.
where x corresponds to the port number (0, 1, or 2).
During normal operation, user code can control the function
and state of the external GPIO pins via these general-purpose
registers. All GPIO pins retain their external high or low during
power-down (POWCON) mode.
REG_DVDD
GPxCON: Portx control register
GPxDAT: Portx configuration and data register
GPxSET: Portx data set
GPxCLR: Portx data clear
GPIO
ADuC7032-8L

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