ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 110

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
Example LIN Hardware Synchronization Routine
Consider the following C-source code LIN initialization routine:
void LIN_INIT(void )
{
}
Using this configuration, LHSVAL1 begins to count on the first
falling edge received on the LIN bus. If LHSVAL1 exceeds the
value written to LHSVAL1, in this case 0x3F, a break compare
interrupt is generated.
On the next falling edge, LHSVAL0 begins counting. LHSVAL0
monitors the number of falling edges and compares this number
to the value written to LHSCON1. In this example, the edge to
monitor is the sixth falling edge of the LIN frame, or the fifth
falling edge of the sync byte.
char HVstatus;
GP2CON = 0x110000;
LHSCON0 = 0x1;
do{
while (!(HVstatus & 0x4));
while((LHSSTA & 0x20) == 0 )
{
}
LHSCON1 = 0x062;
LHSCON0 = 0x0114;
LHSVAL1 = 0x03F;
HVDAT = 0x02;
HVCON = 0x08;
}
do{
while(HVstatus & 0x1); // Wait until command is finished
}
HVstatus = HVCON;
// Enable LHS on GPIO pins
// Reset LHS interface
// Enable normal LIN TX mode
// Write to Config0
// Transmit command is correct
// Wait until the LHS hardware is reset
// Sets stop edge as the fifth falling edge
// and the start edge as the first falling
// edge in the sync byte
// Gates UART RX line, ensure no interference
// from the LIN into the UART
// Selects the stop condition as a falling edge
// Enables generation of an interrupt on the
// stop condition
// Enables the interface
// Set number of 131 kHz periods to generate
// a break interrupt 0x3F / 131 kHz ~ 480 µs
// which is just over 9.5 tbits
Rev. A | Page 110 of 120
After the number of falling edges is received, a stop condition
interrupt is generated. It is at this point that the UART is
configured to receive the protected identifier.
The UART must not be ungated, through LHSCON0[8], before
the LIN bus returns high. If this occurs, UART communication
errors may occur. This process is shown in detail in Figure 46.
Example code follows.