LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 37

• Manufacturer Part Number: LAN89218AQ_samples
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ_samples

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
3.7
3.7.1
3.7.2
3.7.3
3.7.4
32-bit vs. 16-bit Host Bus Width Operation
The LAN89218 can be configured to communicate with the host bus via either a 32-bit or a 16-bit bus.
The external strap D32/nD16 (on the EEDIO pin) is used to select between the two modes. 32-bit
mode is the native environment for the LAN89218 Ethernet controller and no special requirements exist
for communication in this mode. However, when this part is used in the 16-bit mode, two writes or
reads must be performed back to back to properly communicate.
The bus width is set by strapping the EEDIO pin; this setting can be read from bit 2 of the “Hardware
Configuration Register”. Please refer to
on page 93
16-bit Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN89218 disregards the transfer.
16-bit Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN89218 will reset its read counters and restart a new cycle on the next read. The Upper 16 data
pins (D[31:16]) are not driven by the LAN89218 in 16-bit mode. These pins have internal pull-down’s
and the signals are left in a high-impedance state.
Mixed Endian Support
In order to allow flexibility with a range of designs, the LAN89218 supports dynamic bus endianess
selection. Support for big and little endian host byte ordering is provided based on the END_SEL
signal. This signal has the same timing characteristics as FIFO_SEL and the address line input pins.
When END_SEL is low, bus accesses utilize little endian byte ordering. When END_SEL is high, bus
accesses utilize big endian byte ordering. In a typical application, END_SEL may be connected to a
high-order address line, making the endian selection address-based. This highly flexible interface
provides mixed endian access for registers and memory for both PIO and host DMA access. For
example, PIO transfers to/from the host control and status registers can utilize a different byte ordering
than host DMA transactions to/from the receive and transmit data FIFOs.
In addition to mixed endian support, the LAN89218 provides a word swap function, as described in
Section
determines how the Data/Status FIFOs and CSR host access byte ordering is applied.
describes the various operation modes of the endianess and word swap ordering logic.
illustrates the FIFO access byte ordering under various endianess and word swap settings. Refer to
Section 3.7.5
Note: All internal busses of the LAN89218 are 32-bits wide with little endian byte ordering.
Host Bus Operations
3.7.5. The word swap function combined with the endianess select bits described above
for additional information on this register.
for additional details.
DATASHEET
Section 5.3.9, "HW_CFG—Hardware Configuration Register,"
37
Revision 1.3 (02-23-10)
Figure 3.10
Table 3.9