LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 97

• Manufacturer Part Number: LAN89218AQ_samples
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ_samples

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
5.3.12
5.3.13
31:24
23:16
31:14
13:12
BITS
BITS
15:0
10
11
Reserved
TX Status FIFO Used Space (TXSUSED). Indicates the amount of space
in DWORDS used in the TX Status FIFO.
TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes,
available in the TX data FIFO. The application should never write more data
than is available, as indicated by this value.
RESERVED
Power Management Mode (PM_MODE)
into the appropriate Power Management mode. Special care must be taken
when modifying these bits.
Encoding:
00b – D0 (normal operation)
01b – D1 (wake-up frame and magic packet detection are enabled)
10b – D2 (can perform energy detect)
11b – RESERVED - Do not set in this mode
Note: When the LAN89218 is in any of the reduced power modes, a write
RESERVED
PHY Reset (PHY_RST) – Writing a ‘1’ to this bit resets the PHY. The internal
logic automatically holds the PHY reset for a minimum of 100 µs. When the
PHY is released from reset, this bit is automatically cleared. All writes to this
bit are ignored while this bit is high.
TX_FIFO_INF—Transmit FIFO Information Register
This register contains the free space in the transmit data FIFO and the used space in the transmit
status FIFO in the LAN89218.
PMT_CTRL— Power Management Control Register
This register controls the Power Management features. This register can be read while the
LAN89218
Note: The LAN89218 must always be read at least once after power-up, reset, or upon return from
Offset:
Offset:
of any data to the BYTE_TEST register will wake-up the device. DO
NOT PERFORM WRITES TO OTHER ADDRRESSES while the
READY bit in this register is cleared.
a power-saving state or write operations will not function.
is in a power saving mode.
DESCRIPTION
DESCRIPTION
80h
84h
DATASHEET
–
These bits set the LAN89218
97
Size:
Size:
32 bits
32 bits
TYPE
RO
RO
RO
TYPE
RO
RO
SC
SC
Revision 1.3 (02-23-10)
DEFAULT
DEFAULT
1200h
00h
00b
-
0b
-
-