LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 75

• Manufacturer Part Number: LAN89218AQ_samples
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ_samples

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
4.2.5
4.3
4.3.1
4.3.2
MAC
Converter
Converter
NRZI
100M Phase Lock Loop (PLL)
The 100M PLL locks onto reference clock and generates the 125 MHz clock used to drive the 125 MHz
logic and the 100Base-Tx Transmitter.
The receive data path is shown in
100M Receive Input
The MLT-3 from the cable is fed into the PHY (on inputs RXP and RXN) via a 1:1 ratio transformer.
The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-
level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the
ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1 m
and 150 m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
100Base-TX Receive
A/D
MII 25 MHz by 4 bits
RX_CLK
Internal
NRZI
MLT-3
Converter
MLT-3
Magnetics
100M
PLL
Figure 4.2 Receive Data Path
MII
MLT-3
DATASHEET
Figure
125 Mbps Serial
MLT-3
by 4 bits
25 MHz
4.2. Detailed descriptions are given below.
6 bit Data
75
RJ45
Decoder
4B/5B
and BLW Correction
recovery, Equalizer
MLT-3
DSP: Timing
CAT-5
by 5 bits
25 MHz
Descrambler
and SIPO
Revision 1.3 (02-23-10)