LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 76

• Manufacturer Part Number: LAN89218AQ_samples
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ_samples

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.3 (02-23-10)
4.3.3
4.3.4
4.3.5
4.3.6
4.4
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also performs
the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the
incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to
descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE
symbols within a window of 4000 bytes (40 µs). This window ensures that a maximum packet size of
1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-
symbols are detected within this time-period, receive operation is aborted and the descrambler re-
starts the synchronization process.
The descrambler can be bypassed by setting bit 0 of register 31.
Alignment
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream
Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored
and utilized until the next start of frame.
5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The SSD,
/J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD
causes the PHY to assert the internal RX_DV signal, indicating that valid data is available on the
Internal RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the
End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the
PHY to de-assert the internal carrier sense and RX_DV.
These symbols are not translated into data.
Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit
nibbles from the MII at a rate of 2.5 MHz and converts them to a 10 Mbps serial data stream. The
data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto
the twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
10Base-T Transmit
MII (digital)
TX 10M (digital)
10M Transmitter (analog)
10M PLL (analog)
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DATASHEET
76
SMSC LAN89218
Datasheet