28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 122

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

The internal queue is capable of holding 128 descriptors while MUSYCC arbitrates to master the PCI bus and
transfer the descriptors into the Interrupt Queue in shared memory.
As the PCI bus is mastered and after descriptors are transferred to shared memory, MUSYCC updates the
Interrupt Status Descriptor. In making the INTCNT field in the descriptor non-0, MUSYCC asserts the PCI INTA*
signal line.
If, during the transfer of descriptors, the Interrupt Queue in shared memory becomes full, MUSYCC stops
transferring descriptors until the host indicates more descriptors can be written out. MUSYCC indicates it cannot
transfer more descriptors into shared memory by setting the bit field INTFULL in the Interrupt Status Descriptor.
MUSYCC has enough internal space to store 128 additional descriptors.
In cases where both shared memory queue and internal queue are full and new descriptors are generated, those
descriptors are discarded. MUSYCC indicates it has lost interrupts internally by overwriting the bit field ILOST in
the last Interrupt Descriptor in the internal queue. The ILOST indication represents one or more lost descriptors.
5.2.6.3
The host must monitor the INTA* signal line at all times. An assertion on this line signifies the INTCNT filed in the
Interrupt Status Descriptor is non-0. A non-0 INTCNT signifies that Interrupt Descriptors have been written to the
Interrupt Queue in shared memory.
Upon detection of the INTA* assertion, the host must perform a direct read of the Interrupt Status Descriptor from
within MUSYCC. This descriptor provides the offset to the location of the first unserviced descriptor in the queue,
the number of unserviced descriptors, and determines if the queue is full.
The INTCNT field is reset on each read of the Interrupt Status Descriptor. As the INTCNT is reset, the INTA* signal
is deasserted.
The host applies its interrupt service routines to service each of the descriptors. As the host finishes servicing a
number of descriptors, it must write the offset to the location of the next available entry in the Interrupt Queue to the
Interrupt Status Descriptor, NEXTINT. A write to this field indicates to MUSYCC that descriptor locations previously
unserviced now have been serviced, and new descriptors can be written. MUSYCC continues to write to available
space whether the host updates the NEXTINT field or not.
5.2.6.4
A second interrupt signal line, the PCI INTB* signal line, is asserted by MUSYCC when it detects an assertion on
the EBUS EINT* signal line. MUSYCC does not generate descriptors or use the interrupt queue for this condition
because it does not know the source or reason for the interrupt. The reason is external to MUSYCC. This signal
acts as an interrupt line pass-through for devices connected to the EBUS. The EINT* signal line can be tied to
interrupt one or more output pins of one or more peripheral devices. As MUSYCC detects EINT* assertion,
MUSYCC asserts the INTB* towards the host as long as the EINT* remains asserted.
The
28478-DSH-002-E
Figure 5-2
illustrates the operation of EINT*.
NOTE:
INTA* Signal Line
INTB* Signal Line
Preliminary Information / Mindspeed Proprietary and Confidential
After reading the Interrupt Status Descriptor, the host services all unserviced descriptors
(count of INTCNT starting at NEXTINT) in the queue at the time of the read. If the host is
unsuccessful in servicing this set of descriptors, the host must provide an alternate method
of tracking unserviced descriptors. Every read of the status descriptors provides
information only on new descriptors placed in the queue autonomously by MUSYCC since
the last time the status descriptor was read.
Mindspeed Technologies
®
Memory Organization
109