28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 74

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Figure 4-3.
28478-DSH-002-E
GENERAL NOTE:
1. E1 Mode employs 32 time slots (0–31) with 8 bits per time slot (0–7) and 256 bits per frame and one frame every 125 µs—2.048 MHz.
2. 2xE1 mode employs 64 time slots (0–63) with 8 bits per time slot (0–7) and 512 bits per frame and one frame every 125 µs—4.096 MHz.
3. 4xE1 mode employs 128 time slots (0–127) with 8 bits per time slot (0–7) and 1024 bits per frame and one frame every 125 µs—8.192
4. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
5. MUSYCC can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock edge independent of any other
6. Relationships between the various configurations of active edges for the synchronization signal and the data signal are shown using a
7. All received signals (e.g., RSYNC, RDAT, TSYNC) are sampled on the specified clock edge (e.g., RCLK, TCLK). All transmit data signals
8. In configuration (a), synchronization and data signals are sampled or latched on a rising clock edge.
9. In configuration (b), synchronization signal is sampled on a rising clock edge, and the data signal is sampled or latched on a falling clock
10. In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on a rising clock
11. In configuration (d), synchronization and data signals are sampled or latched on a falling clock edge.
MHz.
signal sampling configuration.
common clock signal for receive and transmit operations. Note the relationship between the frame bit (within RDAT, TDAT) and the frame
synchronization signal (e.g., RSYNC, TSYNC).
(TDAT) are latched on the specified clock edge.
edge.
edge.
8478_015
RSYNC-RISE(a)
RSYNC-RISE(b)
RSYNC-FALL(c)
RSYNC-FALL(d)
TSYNC-FALL(d)
RDATA-RISE(a)
TSYNC-RISE(a)
TSYNC-RISE(b)
TDATA-FALL(b)
TSYNC-FALL(c)
TDATA-FALL(d)
RDATA-RISE(c)
RDAT-FALL(b)
RDAT-FALL(d)
TDAT-RISE(a)
TDAT-RISE(c)
Transmit and Receive E1 (also 2xE1, 4xE1) Mode
RCLK
TCLK
Preliminary Information / Mindspeed Proprietary and Confidential
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